ADP3188 Просмотр технического описания (PDF) - Analog Devices
Номер в каталоге
Компоненты Описание
производитель
ADP3188 Datasheet PDF : 28 Pages
| |||
ADP3188
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VID4 1
VID3 2
VID2 3
VID1 4
VID0 5
VID5 6
FBRTN 7
FB 8
COMP 9
PWRGD 10
EN 11
DELAY 12
RT 13
RAMPADJ 14
ADP3188
TOP VIEW
(Not to Scale)
28 VCC
27 PWM1
26 PWM2
25 PWM3
24 PWM4
23 SW1
22 SW2
21 SW3
20 SW4
19 GND
18 CSCOMP
17 CSSUM
16 CSREF
15 ILIMIT
Figure 5. Pin Configuration
Table 3. Pin Function Descriptions
Pin No. Mnemonic Description
1 to 6
VID4 to VID0,
VID5
Voltage Identification DAC Inputs. These six pins are pulled up to an internal reference, providing a Logic 1 if
left open. When in normal operation mode, the DAC output programs the FB regulation voltage from 0.8375 V
to 1.6 V (see Table 4). Leaving all the VID pins open results in the ADP3188 going into No CPU mode, shutting
off its PWM outputs and pulling the PWRGD output low.
7
FBRTN
Feedback Return. VID DAC and error amplifier reference for remote sensing of the output voltage.
8
FB
Feedback Input. Error amplifier input for remote sensing of the output voltage. An external resistor between
this pin and the output voltage sets the no-load offset point.
9
COMP
Error Amplifier Output and Compensation Point.
10
PWRGD
Power Good Output. Open-drain output that signals when the output voltage is outside the proper
operating range.
11
EN
Power Supply Enable Input. Pulling this pin to GND disables the PWM outputs and pulls the PWRGD output low.
12
DELAY
Soft-Start Delay and Current-Limit Latch-Off Delay Setting Input. An external resistor and capacitor connected
between this pin and GND sets the soft-start ramp-up time and the overcurrent latch-off delay time.
13
RT
Frequency Setting Resistor Input. An external resistor connected between this pin and GND sets the oscillator
frequency of the device.
14
RAMPADJ
PWM Ramp Current Input. An external resistor from the converter input voltage to this pin sets the internal
PWM ramp.
15
ILIMIT
Current-Limit Setpoint/Enable Output. An external resistor from this pin to GND sets the current-limit threshold
of the converter. This pin is actively pulled low when the ADP3188 EN input is low, or when VCC is below its
UVLO threshold, to signal to the driver IC that the driver high-side and low-side outputs should go low.
16
CSREF
Current-Sense Reference Voltage Input. The voltage on this pin is used as the reference for the current-sense
amplifier and the power good and crowbar functions. This pin should be connected to the common point of
the output inductors.
17
CSSUM
Current-Sense Summing Node. External resistors from each switch node to this pin sum the average inductor
currents together to measure the total output current.
18
CSCOMP
Current-Sense Compensation Point. A resistor and a capacitor from this pin to CSSUM determine the slope of
the load line and the positioning loop response time.
19
GND
Ground. All internal biasing and the logic output signals of the device are referenced to this ground.
20 to 23 SW4 to SW1 Current-Balance Inputs. Inputs for measuring the current level in each phase. The SW pins of unused phases
should be left open.
24 to 27 PWM4 to
PMW1
Logic-Level PWM Outputs. Each output is connected to the input of an external MOSFET driver such as the
ADP3418. Connecting the PWM3 and/or PWM4 outputs to GND causes that phase to turn off, allowing the
ADP3188 to operate as a 2-, 3-, or 4-phase controller.
28
VCC
Supply Voltage for the Device.
Rev. A | Page 7 of 28
Share Link: 