ADP3188 Просмотр технического описания (PDF) - Analog Devices
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ADP3188 Datasheet PDF : 28 Pages
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6-Bit Programmable 2-/3-/4-Phase
Synchronous Buck Controller
ADP3188
FEATURES
Selectable 2-, 3- or 4-phase operation at up to
1 MHz per phase
±9.5 mV worst-case differential sensing error over
temperature
Logic-level PWM outputs for interface to external
high power drivers
Active current balancing between all output phases
Built-in power good/crowbar blanking supports on-the-fly
VID code changes
6-bit digitally programmable 0.8375 V to 1.6 V output
Programmable short-circuit protection with
programmable latch-off delay
APPLICATIONS
Desktop PC power supplies for
Next-generation Intel® processors
VRM modules
GENERAL DESCRIPTION
The ADP3188 is a highly efficient, multiphase, synchronous
buck switching regulator controller optimized for converting a
12 V main supply into the core supply voltage required by high
performance Intel processors. The part uses an internal 6-bit
DAC to read a voltage identification (VID) code directly from
the processor, which is used to set the output voltage between
0.8375 V and 1.6 V. It uses a multimode PWM architecture to
drive the logic-level outputs at a programmable switching
frequency that can be optimized for VR size and efficiency.
The phase relationship of the output signals can be pro-
grammed to provide 2-, 3-, or 4-phase operation, allowing
the construction of up to four complementary buck
switching stages.
The ADP3188 also includes programmable no-load offset and
slope functions to adjust the output voltage as a function of
the load current, so it is always optimally positioned for a system
transient. The ADP3188 also provides accurate and reliable
short-circuit protection, adjustable current limiting, and a
delayed power good output that accommodates on-the-fly
output voltage changes requested by the CPU.
The ADP3188 is specified over the commercial tempera-
ture range of 0°C to 85°C and is available in 28-lead, TSSOP
and QSOP packages.
EN 11
GND 19
FUNCTIONAL BLOCK DIAGRAM
VCC
28
UVLO
SHUTDOWN
AND BIAS
RAMPADJ RT
14
13
ADP3188
OSCILLATOR
SET EN
CMP RESET
27 PWM1
DAC+150mV
CSREF
DAC-250mV
PWRGD 10
DELAY
CURRENT
BALANCING
CIRCUIT
CMP
CMP
RESET
2-/3-/4-PHASE
DRIVER LOGIC
RESET
26 PWM2
25 PWM3
CMP RESET
CROWBAR
24 PWM4
CURRENT
LIMIT
ILIMIT 15
EN
DELAY 12
SOFT
START
CURRENT
LIMIT
CIRCUIT
23 SW1
22 SW2
21 SW3
20 SW4
17 CSSUM
16 CSREF
18 CSCOMP
COMP 9
8 FB
PRECISION
REFERENCE
VID
DAC
7
FBRTN
1 23456
VID4 VID3 VID2 VID1 VID0 VID5
Figure 1.
Rev. A
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Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved.
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