ADP3182JRQZ-RL Просмотр технического описания (PDF) - Analog Devices
Номер в каталоге
Компоненты Описание
производитель
ADP3182JRQZ-RL Datasheet PDF : 20 Pages
| |||
ADP3182
PIN CONFIGURATION AND FUNCTION DESCRIPTION
VCC 1
FBRTN 2
FB 3
COMP 4
PWRGD 5
EN 6
DELAY 7
RT 8
RAMPADJ 9
ILIMIT 10
ADP3182
TOP VIEW
(Not to Scale)
20 PWM1
19 PWM2
18 PWM3
17 SW1
16 SW2
15 SW3
14 GND
13 CSCOMP
12 CSSUM
11 CSREF
Figure 3. Pin Configuration
Table 3. Pin Function Descriptions
Pin No. Mnemonic Description
1
VCC
Supply Voltage for the Device.
2
FBRTN
Feedback Return. Voltage error amplifier reference for remote sensing of the output voltage.
3
FB
Feedback Input. Error amplifier input for remote sensing of the output voltage. An external resistor divider
between the output and FBRTN connected to this pin sets the output voltage point. This pin is also the reference
point for the power good and crowbar comparators.
4
COMP
Error Amplifier Output and Compensation Point.
5
PWRGD
Power Good Output. Open-drain output that signals when the output voltage is outside the proper operating
range.
6
EN
Power Supply Enable Input. Pulling this pin to GND disables the PWM outputs and pulls the PWRGD output low.
7
DELAY
Soft Start Delay and Current Limit Latch-Off Delay Setting Input. An external resistor and capacitor connected
between this pin and GND sets the soft start, ramp-up time and the overcurrent latch-off delay time.
8
RT
Frequency Setting Resistor Input. An external resistor connected between this pin and GND sets the oscillator
frequency of the device.
9
RAMPADJ PWM Ramp Current Input. An external resistor from the converter input voltage to this pin sets the internal
PWM ramp.
10
ILIMIT
Current Limit Setpoint/Enable Output. An external resistor from this pin to GND sets the current limit threshold
of the converter. This pin is actively pulled low when the ADP3182’s EN input is low, or when VCC is below its
UVLO threshold, to signal to the driver IC that the driver high-side and low-side outputs should go low.
11
CSREF
Current Sense Reference Voltage Input. The voltage on this pin is used as the reference for the current sense
amplifier. This pin should be connected to the common point of the output inductors.
12
13
14
15 to 17
18 to 20
CSSUM
CSCOMP
GND
SW3 to SW1
PWM3 to
PMW1
Current Sense Summing Node. External resistors from each switch node to this pin sum the average inductor
currents together to measure the total output current.
Current Sense Compensation Point. A resistor and a capacitor from this pin to CSSUM determines the gain of the
current sense amplifier.
Ground. All internal biasing and the logic output signals of the device are referenced to this ground.
Current Balance Inputs. Inputs for measuring the current level in each phase. The SW pins of unused phases
should be left open.
Logic-Level PWM Outputs. Each output is connected to the input of an external MOSFET driver such as the
ADP3418. Connecting the PWM3 output to GND causes that phase to turn off, allowing the ADP3182 to operate
as a 1- or 2-phase controller.
Rev. 0 | Page 7 of 20
Share Link: 