ADP3181JRUZ-REEL Просмотр технического описания (PDF) - Analog Devices
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ADP3181JRUZ-REEL Datasheet PDF : 24 Pages
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ADP3181
THEORY OF OPERATION
The ADP3181 combines a multimode, fixed-frequency PWM
control with multiphase logic outputs for use in 2-, 3-, and
4-phase synchronous buck CPU core supply power converters.
The internal VID DAC can be used in Intel’s 5-bit VRM 9 or
6-bit VRD/VRM 10 designs, depending on the setting of the
CPUID pin. Multiphase operation is important for producing
the high currents and low voltages demanded by today’s micro-
processors. Handling the high currents in a single-phase
converter places high thermal demands on the components in
the system such as the inductors and MOSFETs. The multimode
control of the ADP3181 ensures a stable, high performance
topology for
• Balancing currents and thermals between phases.
• High speed response at the lowest possible switching
frequency and output decoupling.
• Minimizing thermal switching losses due to lower
frequency operation.
• Tight load line regulation and accuracy.
• High current output from 4-phase operational design.
• Reduced output ripple due to multiphase cancellation.
• PC board layout noise immunity.
• Ease of use and design due to independent component
selection.
• Flexibility in operation for tailoring design to low cost or
high performance.
START-UP SEQUENCE
Two functions are set during the start-up sequence: the number
of active phases and the VID DAC configuration. The number
of operational phases and their phase relationship is determined
by internal circuitry that monitors the PWM outputs. Normally,
the ADP3181 operates as a 4-phase PWM controller. Grounding
the PWM4 pin programs 3-phase operation and grounding the
PWM3 and PWM4 pins programs 2-phase operation.
When the ADP3181 is enabled, the controller outputs a voltage
on PWM3 and PWM4 that is approximately 675 mV. An
internal comparator checks each pin’s voltage versus a threshold
of 300 mV. If the pin is grounded, then it is below the threshold
and the phase is disabled. The output resistance of the PWM
pin is approximately 5 kΩ during this detection time. Any
external pull-down resistance connected to the PWM pin
should not be less than 25 kΩ to ensure proper operation.
PWM1 and PWM2 are disabled during the phase detection
interval, which occurs during the first two clock cycles of the
internal oscillator. After this time, if the PWM output is not
grounded the 5 kΩ resistance is removed and it switches
between 0 V and 5 V. If the PWM output is grounded then it
remains off.
The PWM outputs are logic-level devices intended for driving
external gate drivers such as the ADP3110. Because each phase
is monitored independently, operation approaching 100% duty
cycle is possible. Also, more than one output can be on at a time
for overlapping phases.
The VID DAC configuration is determined by the voltage pre-
sent at the CPUID pin. If this pin is pulled up to >4.5 V, the
VID DAC operates with five inputs and generates the VR 9
output voltage range, as shown in Table 4. If CPUID is <4 V, the
VID DAC treats CPUID as the VID5 input of VR 10 and
operates as a 6-bit DAC using the output voltage range given in
Table 5.
Table 4. VR 9 VID Codes for ADP3181JRU Only, CPUID >4.25
VID4 VID3 VID2 VID1 VID0 Output
1
1
1
1
1
No CPU
1
1
1
1
0
1.100 V
1
1
1
0
1
1.125 V
1
1
1
0
0
1.150 V
1
1
0
1
1
1.175 V
1
1
0
1
0
1.200 V
1
1
0
0
1
1.225 V
1
1
0
0
0
1.250 V
1
0
1
1
1
1.275 V
1
0
1
1
0
1.300 V
1
0
1
0
1
1.325 V
1
0
1
0
0
1.350 V
1
0
0
1
1
1.375 V
1
0
0
1
0
1.400 V
1
0
0
0
1
1.425 V
1
0
0
0
0
1.450 V
0
1
1
1
1
1.475 V
0
1
1
1
0
1.500 V
0
1
1
0
1
1.525 V
0
1
1
0
0
1.550 V
0
1
0
1
1
1.575 V
0
1
0
1
0
1.600 V
0
1
0
0
1
1.625 V
0
1
0
0
0
1.650 V
0
0
1
1
1
1.675 V
0
0
1
1
0
1.700 V
0
0
1
0
1
1.725 V
0
0
1
0
0
1.750 V
0
0
0
1
1
1.775 V
0
0
0
1
0
1.800 V
0
0
0
0
1
1.825 V
0
0
0
0
0
1.850 V
Rev. A | Page 9 of 24
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