ADP3088(RevC) Просмотр технического описания (PDF) - Analog Devices

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ADP3088
(Rev.:RevC)

1 MHz, 750 mA Buck Regulator

Analog Devices 

ADP3088

output voltage has been developed. (The circuit in Figure 3

higher than VREF, which would result in a slight downward shift

with a –3.3 V output works well over an input range from 2.5 V of the nominal output voltage.

to 7.5 V.) Since the ADP3088 features a current-controlled

loop, the feedback effect of essentially boosting the input voltage

atop the output (with respect to the ground connection of the

ADP3088) is reduced to a negligible second-order effect.

Having chosen this design approach, the series RC of the com-

pensation network can be removed, and the single remaining

capacitor, CHF, should be increased to approximately

VIN

5V

1␮F

MLCC

ADP3088

IN

SW

IN

DRV

GND GND

4.7␮H

1A

10␮F

SCHOTTKY MLCC

+

RA

10k⍀

CHF

=

CO ¥ ESR

RFB

(18)

If an MLC capacitor is used for CO, the value of CHF might be

calculated to be less than a few picofarads, in which case it is

recommended to use a 4.7 pF~10 pF capacitor. The formula is

CHF

4.7pF

COMP FB

CC

220pF

RC

20k⍀

+

RB

6.04k⍀

VOUT

– 3.3V

Figure 3. +5 V to –3.3 V, General-Purpose

E Inverting Application

Voltage Positioning Designs

For digital loads, a different compensation technique is recom-

mended that involves implementing “voltage positioning,”

T which is now commonly used on CPUs but is equally applicable

to any dynamic device. Voltage positioning is the intentional

and controlled variation of the output voltage with the load

current, such that the power supply appears to have a sub-

E stantial output resistance. The key to voltage positioning

optimization for a digital load is to degenerate the loop gain

just enough so that the static load regulation allows a similar

L voltage deviation with the current as would be the peak volt-

age deviation, ⌬VO, that could not be avoided in the event

that a step change of the current were to occur even if the

loop response were instantaneous. The reason for even an

instantaneous response in the control loop allowing an output

O voltage deviation is that the slew rate of the current in the

output is limited by the inductor, and a corresponding dynamic

burden is placed on the output capacitor to maintain the output

voltage. Therefore, inductor value minimization is desired both

S for concern over its size and cost and also to maximize the slew

rate of the current to the output so that a smaller output capaci-

tor is needed.

B To implement voltage positioning, a resistor, RVP, should be placed

between the COMP and FB pins according to the formula

O RVP

=

DIO RA

gMOD ¥ DVO

(17)

derived from a patented design technique called ADOPT®,

Analog Devices’ Optimal Positioning Technology. This creates

ac and dc impedance matching, and the increased complexity of

the dc regulation design is moderated by the simplicity of the

frequency compensation.

In this design approach, at higher currents the output voltage

will be appreciably lower than at the lower currents. This is equiva-

lent to saying that the load regulation appears to be poor.

But, paradoxically perhaps to the user unfamiliar with volt-

age positioning, the overall containment of the voltage within a

given window will be improved, and that tends to be of particu-

lar importance in many highly dynamic loads.

The application circuit in Figure 4 features a 3.3 V input and a

2.5 V output at 100 mA~400 mA, which constrains the output

voltage within a ~100 mV range with only a 4.7 mF output

capacitor, even when the load slew rate is extremely fast. This

does not include the initial tolerance of the voltage setting

that is separately accounted with voltage positioning designs.

Note that the lower resistor, RB, of the feedback divider is

reduced from the 10 kW value that one would use for a standard

(nonvoltage-positioned) design that had no voltage positioning

resistor RVP.

VIN

3.3V

1␮F

MLCC

CHF

4.7pF

ADP3088

IN

SW

IN

DRV

GND GND

COMP FB

RVP

51k⍀

3.3␮H

1A

4.7␮F

SCHOTTKY MLCC

VOUT

2.5V

100 mA– 400 mA

RA

10k⍀

RB

8.75k⍀

Figure 4. Application Circuit Using Voltage Posi-

tioning, Allowing Small Output Capacitance

where gMOD is the modulator gain and ⌬IO must be assessed

over the entire operating load range as the difference between

the maximum and minimum load. CO must be chosen at least

large enough to support the targeted ⌬VO according to the previous

formula governing the relationship among the minimum output

capacitance, voltage deviation, and load current. In order to ensure

that the output voltage will be constrained within the limitations

of ⌬VO, the limitations noted earlier for PSM hysteretic ripple are

applicable in the operating load range and ESR. Also, an experi-

mental adjustment downward to the value of RB may be needed,

since the dc bias point of the COMP node is usually a little

Extra-Low Voltage Outputs

Some newer power management applications require voltage levels

below the normal adjustable voltage range of the ADP3088, i.e.,

below 1.25 V. Such applications can be accommodated using

the ADP3088 by modifying the application circuit to sum in a

resistor-weighted portion of another regulated system voltage,

e.g., 3.3 V, to the feedback node (FB). The tolerance of the

ADP3088’s output voltage will increase by an amount propor-

tional to the tolerance of the summed in-system voltage times

the ratio of the conductance from that node to that of the output

voltage. The example in Figure 5 shows an implementation

of this technique together with another special implementation

described in the following section. The resistor RTT sums from a

REV. C

–13–

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