ADM1186-1ARQZ Просмотр технического описания (PDF) - Analog Devices
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ADM1186-1ARQZ Datasheet PDF : 28 Pages
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ADM1186
Data Sheet
Pin No.
ADM1186-1 ADM1186-2
12
9
13
10
14
15
11
16
12
17
13
18
14
19
15
20
16
Mnemonic
DLY_EN_OUT4
BLANK_DLY
SEQ_DONE
PWRGD
OUT4
OUT3
OUT2
OUT1
VCC
Description
Timing Input. The capacitor connected to this input sets the time delay between VIN3
coming into compliance and OUT4 being asserted high during a power-up sequence.
During a power-down sequence, this input sets the time delay between OUT4 being
asserted low and OUT3 being asserted low.
Timing Input. The capacitor connected to this input sets the blanking time. This is the
time allowed between OUTx being asserted and VINx coming into compliance; otherwise,
the SET FAULT state is entered.
Active High, Open-Drain Output. This output is pulled low when VCC = 1 V. When the
power-up sequence is complete, SEQ_DONE is asserted high. During a power-down
sequence, the pin remains asserted until the time delay set by DLY_EN_OUT1 has
elapsed. When a fault occurs, this pin is asserted low.
Active High, Open-Drain Output. This output is pulled low when VCC = 1 V. The output
state of this pin is a logical AND function of the UV threshold state of the VINx pins. When
the voltage on all VINx inputs exceeds 0.6 V, PWRGD is asserted. This output is driven low
if the voltage on any VINx pin is below 0.6 V.
Active High, Open-Drain Output. This output is pulled low when VCC = 1 V. During a
power-up sequence, this output is asserted high after the time delay set by the capacitor
on DLY_EN_OUT4 has elapsed. The output is asserted low immediately after a power-
down sequence has been initiated.
Active High, Open-Drain Output. This output is pulled low when VCC = 1 V. During a
power-up sequence, this output is asserted high after the time delay set by the capacitor
on DLY_EN_OUT3 has elapsed. During a power-down sequence, the output is asserted
low after the time delay set by the capacitor on DLY_EN_OUT4 has elapsed.
Active High, Open-Drain Output. This output is pulled low when VCC = 1 V. During a
power-up sequence, this output is asserted high after the time delay set by the capacitor
on DLY_EN_OUT2 has elapsed. During a power-down sequence, the output is asserted
low after the time delay set by the capacitor on DLY_EN_OUT3 has elapsed.
Active High, Open-Drain Output. This output is pulled low when VCC = 1 V. During a
power-up sequence, this output is asserted high after the time delay set by the capacitor
on DLY_EN_OUT1 has elapsed (ADM1186-1) or immediately after a rising edge on
UP/DOWN (ADM1186-2). During a power-down sequence, the output is asserted low
after the time delay set by the capacitor on DLY_EN_OUT2 has elapsed.
Positive Supply Input Pin. The operating supply voltage range is 2.7 V to 5.5 V.
Rev. B | Page 8 of 28
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