ADG3308BRUZ-REEL7 Просмотр технического описания (PDF) - Analog Devices

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ADG3308BRUZ-REEL7

Low Voltage, 1.15 V to 5.5 V, 8-Channel Bidirectional Logic Level Translators

Analog Devices 

ADG3308/ADG3308-1

APPLICATIONS

The ADG3308/ADG3308-1 are designed for digital circuits

that operate at different supply voltages; therefore, logic level

translation is required. The lower voltage logic signals are

connected to the A pins, and the higher voltage logic signals

to the Y pins. The ADG3308/ADG3308-1 can provide level

translation in both directions (A→Y or Y→A) on all eight

channels, eliminating the need for a level translator IC for

each direction. The internal architecture allows the ADG3308/

ADG3308-1 to perform bidirectional level translation without

an additional signal to set the direction in which the translation

is made. It also allows simultaneous data flow in both directions

on the same part, for example, when two channels translate in the

A→Y direction while the other two translate in the Y→A

direction. This simplifies the design by eliminating the timing

requirements for the direction signal and reduces the number of

ICs used for level translation.

Figure 40 shows an application where a 3.3 V microprocessor

can read or write data to and from a 1.8 V peripheral device

using an 8-bit bus.

3.3V

I/OH1

100nF

100nF

VCCY VCCA

Y1

A1

ADG3308/

ADG3308-1

1.8V

I/OL1

I/OH2

I/OH3

Y2

A2

Y3

A3

I/OL2

I/OL3

I/OH4

I/OH5

Y4

A4

Y5

A5

I/OL4

I/OL5

I/OH6

Y6

A6

I/OL6

I/OH7

Y7

A7

I/OL7

I/OH8

Y8

A8

I/OL8

GND

EN

GND

GND

Figure 40. 1.8 V to 3.3 V 8-Bit Level Translation Circuit

When the application requires level translation between

a microprocessor and multiple peripheral devices, the

ADG3308/ADG3308-1 I/O pins can be three-stated by setting

EN = 0. This feature allows the ADG3308/ADG3308-1 to share

the data buses with other devices without causing contention

issues. Figure 41 shows an application where a 3.3 V micro-

processor is connected to 1.8 V peripheral devices using the

three-state feature.

Data Sheet

3.3V

I/OH1

I/OH2

I/OH3

I/OH4

I/OH5

I/OH6

I/OH7

I/OH8

GND CS

100nF

100nF

ADG3308/

ADG3308-1

VCCY

Y1

Y2

Y3

Y4

Y5

Y6

Y7

Y8

EN

VCCA

A1

A2

A3

A4

A5

A6

A7

A8

GND

1.8V

I/OL1

I/OL2

I/OL3

I/OL4

I/OL5

I/OL6

I/OL7

I/OL8

GND

100nF

100nF

ADG3308/

ADG3308-1

VCCY

Y1

Y2

Y3

Y4

Y5

Y6

Y7

Y8

EN

VCCA

A1

A2

A3

A4

A5

A6

A7

A8

GND

1.8V

I/OL1

I/OL2

I/OL3

I/OL4

I/OL5

I/OL6

I/OL7

I/OL8

GND

Figure 41. 1.8 V to 3.3 V Level Translation Circuit

Using the Three-State Feature

LAYOUT GUIDELINES

As with any high speed digital IC, the printed circuit board

layout is important in the overall performance of the circuit. Care

should be taken to ensure proper power supply bypass and

return paths for the high speed signals. Each VCC pin (VCCA and

VCCY) should be bypassed using low effective series resistance

(ESR) and effective series inductance (ESI) capacitors placed as

close as possible to the VCCA and VCCY pins. The parasitic induc-

tance of the high speed signal track can cause significant overshoot.

This effect can be reduced by keeping the length of the tracks as

short as possible. A solid copper plane for the return path

(GND) is also recommended.

Rev. D | Page 18 of 20

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