Data Sheet
AD9645
VINx±
CLK–
CLK+
DCO–
DCO+
FCO–
FCO+
D0x–
D0x+
N–1
tA
tEH
tCPD
N
tEL
tFCO
tFRAME
tPD
tDATA
MSB D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1 LSB
0
0 MSB D14 D13
N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 16 N – 16 N – 16
Figure 6. Wordwise DDR, One-Lane, 1× Frame, 16-Bit Output Mode
VINx±
CLK–
CLK+
DCO–
DCO+
FCO–
FCO+
D0x–
D0x+
N–1
tA
tEH
tCPD
N
tEL
tFCO
tFRAME
tPD
tDATA
MSB D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0 MSB D10
N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 16 N – 16
Figure 7. Wordwise DDR, One-Lane, 1× Frame, 12-Bit Output Mode
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