AD9643BCPZ-170(RevE) Просмотр технического описания (PDF) - Analog Devices
Номер в каталоге
Компоненты Описание
производитель
AD9643BCPZ-170
(Rev.:RevE)
(Rev.:RevE)
Analog Devices
AD9643BCPZ-170 Datasheet PDF : 36 Pages
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AD9643
Timing Diagrams
VIN
CLK+
CLK–
DCO–
DCO+
PARALLEL INTERLEAVED
D0±
(LSB)
.
CHANNEL A AND .
CHANNEL B .
D13±
(MSB)
N–1
tCH
Data Sheet
tA
N
N+1
tCLK
N+2
N+3
N+4
N+5
tDCO
tSKEW
tPD
CH A CH B
N – 10 N – 10
CH A
N–9
CH B
N–9
CH A
N–8
CH B
N–8
CH A
N–7
CH B
N–7
CH A
N–6
CH A CH B
N – 10 N – 10
CH A
N–9
CH B
N–9
CH A
N–8
CH B
N–8
CH A
N–7
CH B
N–7
CH A
N–6
CHANNEL MULTIPLEXED D0±/D1±
(EVEN/ODD) MODE (LSB)
.
CHANNEL A
.
.
D12±/D13±
(MSB)
CHANNEL MULTIPLEXED D0±/D1±
(EVEN/ODD) MODE (LSB)
.
CHANNEL B ..
D12±/D13±
(MSB)
CLK+
SYNC
CH A0 CH A1
N – 10 N – 10
CH A0
N–9
CH A1
N–9
CH A0 CH A1
N–8 N–8
CH A0
N–7
CH A1
N–7
CH A0
N–6
CH A12 CH A13 CH A12 CH A13 CH A12 CH A13 CH A12 CH A13 CH A12
N – 10 N – 10 N – 9
N–9
N–8
N–8
N–7
N–7
N–6
CH B0 CH B1
N – 10 N – 10
CH B0
N–9
CH B1
N–9
CH B0 CH B1
N–8 N–8
CH B0
N–7
CH B1
N–7
CH B0
N–6
CH B12 CH B13 CH B12 CH B13 CH B12 CH B13 CH B12 CH B13 CH B12
N – 10 N – 10 N – 9
N–9
N–8
N–8
N–7
N–7
N–6
Figure 2. LVDS Modes for Data Output Timing
tSSYNC
tHSYNC
Figure 3. SYNC Timing Inputs
Rev. E | Page 10 of 36
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