AD9553BCPZ(Rev0) Просмотр технического описания (PDF) - Analog Devices
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Компоненты Описание
производитель
AD9553BCPZ
(Rev.:Rev0)
(Rev.:Rev0)
Analog Devices
AD9553BCPZ Datasheet PDF : 44 Pages
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AD9553
OUTPUT CHARACTERISTICS
Table 8.
Parameter
LVPECL MODE
Differential Output Voltage
Swing
Common-Mode Output
Voltage
Frequency Range
Duty Cycle
Rise/Fall Time1 (20% to 80%)
LVDS MODE
Differential Output Voltage
Swing
Balanced, VOD
Unbalanced, ΔVOD
Offset Voltage
Common Mode, VOS
Common-Mode Difference,
ΔVOS
Short-Circuit Output Current
Frequency Range
Duty Cycle
Rise/Fall Time1 (20% to 80%)
CMOS MODE
Output Voltage High, VOH
IOH = 10 mA
IOH = 1 mA
Output Voltage Low, VOL
IOL = 10 mA
IOL = 1 mA
Frequency Range
Duty Cycle
Rise/Fall Time1 (20% to 80%)
Min
Typ
Max
Unit
690
800
890
mV
VDD − 1.66 VDD − 1.34 VDD − 1.01 V
0
810
MHz
40
60
%
255
305
ps
297
398
mV
8.3
mV
1.17
1.35
V
7.3
mV
17
24
mA
0
810
MHz
40
60
%
285
355
ps
2.8
V
2.8
V
0.5
V
0.3
V
0
200
MHz
45
55
%
500
745
ps
Test Conditions/Comments
Output driver static (for dynamic performance, see Figure 13).
Output driver static.
Up to 805 MHz output frequency.
100 Ω termination between the output driver pins.
Output driver static (for dynamic performance, see Figure 13).
Voltage swing between output pins; output driver static.
Absolute difference between voltage swing of normal pin and
inverted pin; output driver static.
Output driver static.
Voltage difference between output pins; output driver static.
Up to 805 MHz output frequency.
100 Ω termination between the output driver pins.
Output driver static; standard drive strength setting.
Output driver static; standard drive strength setting.
3.3 V CMOS; standard drive strength setting. Output toggle
rates in excess of the maximum are possible, but with reduced
amplitude (see Figure 12).
At maximum output frequency.
3.3 V CMOS; standard drive strength setting; 10 pF load.
1 The listed values are for the slower edge (rise or fall).
Rev. 0 | Page 6 of 44
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