AD9550 Просмотр технического описания (PDF) - Analog Devices

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производитель

AD9550

1.2Ghz Clock Distribution IC / PLL Core / Divider / Delay Adjust / 8 Outputs

Analog Devices 

AD9550

SPECIFICATIONS

Minimum (min) and maximum (max) values apply for the full range of supply voltage and operating temperature variations. Typical (typ)

values apply for VDD = 3.3 V; TA = 25°C, unless otherwise noted.

Table 1.

Parameter

SUPPLY VOLTAGE

POWER CONSUMPTION

Total Current

VDD Current By Pin

Pin 18

Pin 21

LVDS Configured Output

LVPECL Configured Output

CMOS Configured Output

Pin 28

LVDS Configured Output

LVPECL Configured Output

CMOS Configured Output

LOGIC INPUT PINS

Input Characteristics1

Logic 1 Voltage, VIH

Logic 0 Voltage, VIL

Logic 1 Current, IIH

Logic 0 Current, IIL

LOGIC OUTPUT PINS

Output Characteristics

Output Voltage High, VOH

Output Voltage Low, VOL

RESET Pin

Input Characteristics2

Input Voltage High, VIH

Input Voltage Low, VIL

Input Current High, IINH

Input Current Low, IINL

Minimum Pulse Width Low

Min Typ Max Unit

3.135 3.30 3.465 V

162 185 mA

93 106 mA

35 41

mA

36 42

mA

29 34

mA

35 41

mA

36 42

mA

29 34

mA

Test Conditions/Comments

Pin 18, Pin 21, and Pin 28

Tested with both output channels active at maximum

output frequency; LVPECL and LVDS outputs use a 100 Ω

termination between both pins of the output driver

1.02

V

For the CMOS inputs, a static Logic 1 results from either

a pull-up resistor or no connection

0.64 V

3

µA

17

µA

Tested at 1 mA load current

2.7

V

0.19 V

1.96

V

0.85 V

0.3 12.5 µA

31 43

µA

150

µs

Tested with an active source driving the RESET pin

REFERENCE CLOCK INPUT CHARACTERISTICS

CMOS Single-Ended Input

Input Frequency Range

0.008

200 MHz

Input High Voltage

1.62

V

Input Low Voltage

0.52 V

Input Threshold Voltage

1.0

V

Input High Current

Input Low Current

Input Capacitance

Duty Cycle

0.04

µA

0.03

µA

3

pF

Pulse Width Low

2

ns

Pulse Width High

2

ns

When ac coupling to the input receiver, the user must

dc bias the input to 1 V

Pulse width high and pulse width low establish the

bounds for duty cycle

Rev. 0 | Page 3 of 20

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