AD9514 HTML VIEW PDF DOWNLOAD, AD9514 Даташит, даташитов

AD9514 Просмотр технического описания (PDF) - Analog Devices

Номер в каталоге

Компоненты Описание

производитель

AD9514

1.2Ghz Clock Distribution IC / PLL Core / Divider / Delay Adjust / 8 Outputs

Analog Devices

AD9514 Datasheet PDF : 28 Pages

1 2 3 4 5 6 7 8 9 10 Next Last

AD9514

Parameter

S0 = 1

Zero Scale Delay Time3

Zero Scale Variation with Temperature

Full Scale Time Delay3

Full Scale Variation with Temperature

Linearity, DNL

Linearity, INL

Min Typ Max Unit Test Conditions/Comments

0.56

0.47

ps/°C

11.4

−5

ps/°C

0.2

LSB

0.2

LSB

1 This is the difference between any two similar delay paths within a single device operating at the same voltage and temperature.

2 This is the difference between any two similar delay paths across multiple devices operating at the same voltage and temperature.

3 Incremental delay; does not include propagation delay.

CLOCK OUTPUT PHASE NOISE

CLK input slew rate = 1 V/ns or greater.

Table 4.

Parameter

CLK-TO-LVPECL ADDITIVE PHASE NOISE

CLK = 622.08 MHz, OUT = 622.08 MHz

Divide = 1

@ 10 Hz Offset

@ 100 Hz Offset

@ 1 kHz Offset

@ 10 kHz Offset

@ 100 kHz Offset

>1 MHz Offset

CLK = 622.08 MHz, OUT = 155.52 MHz

Divide = 4

@ 10 Hz Offset

@ 100 Hz Offset

@ 1 kHz Offset

@ 10 kHz Offset

@ 100 kHz Offset

>1 MHz Offset

CLK = 622.08 MHz, OUT = 38.88 MHz

Divide = 16

@ 10 Hz Offset

@ 100 Hz Offset

@ 1 kHz Offset

@ 10 kHz Offset

@ 100 kHz Offset

>1 MHz Offset

CLK = 491.52 MHz, OUT = 61.44 MHz

Divide = 8

@ 10 Hz Offset

@ 100 Hz Offset

@ 1 kHz Offset

@ 10 kHz Offset

@ 100 kHz Offset

>1 MHz Offset

Min Typ

Max Unit

Test Conditions/Comments

−125

−132

−140

−148

−153

−154

−128

−140

−148

−155

−161

−135

−145

−158

−165

−166

−131

−142

−153

−160

−165

dBc/Hz

Rev. 0 | Page 5 of 28

Share Link: