AD9273 Просмотр технического описания (PDF) - Analog Devices
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AD9273 Datasheet PDF : 48 Pages
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AD9273
SWITCHING SPECIFICATIONS
AVDD1 = 1.8 V, AVDD2 = 3.0 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, fIN = 5 MHz, full temperature, unless otherwise noted.
Table 3.
Parameter1
CLOCK2
Clock Rate
Clock Pulse Width High (tEH)
Clock Pulse Width Low (tEL)
OUTPUT PARAMETERS2, 3
Propagation Delay (tPD)
Rise Time (tR) (20% to 80%)
Fall Time (tF) (20% to 80%)
FCO± Propagation Delay (tFCO)
DCO± Propagation Delay (tCPD)4
DCO± to Data Delay (tDATA)4
DCO± to FCO± Delay (tFRAME)4
Data-to-Data Skew
(tDATA-MAX − tDATA-MIN)
Wake-Up Time (Standby), GAIN+ = 0.8 V
Wake-Up Time (Power-Down)
Pipeline Latency
APERTURE
Aperture Uncertainty (Jitter)
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
25°C
25°C
Full
25°C
Min
10
(tSAMPLE/2) + 1.5
(tSAMPLE/2) + 1.5
(tSAMPLE/24) − 300
(tSAMPLE/24) − 300
Typ
10
10
(tSAMPLE/2) + 2.3
300
300
(tSAMPLE/2) + 2.3
tFCO + (tSAMPLE/24)
(tSAMPLE/24)
(tSAMPLE/24)
±100
<2
1
8
<1
Max
50
(tSAMPLE/2) + 3.1
(tSAMPLE/2) + 3.1
(tSAMPLE/24) + 300
(tSAMPLE/24) + 300
±350
Unit
MSPS
ns
ns
ns
ps
ps
ns
ns
ps
ps
ps
μs
ms
Clock cycles
ps rms
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.
2 Can be adjusted via the SPI.
3 Measurements were made using a part soldered to FR-4 material.
4 tSAMPLE/24 is based on the number of bits divided by 2 because the delays are based on half duty cycles.
Rev. B | Page 9 of 48
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