AD9269(Rev0) Просмотр технического описания (PDF) - Analog Devices
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AD9269 Datasheet PDF : 40 Pages
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AD9269
MEMORY MAP REGISTER TABLE
All address and bit locations that are not included in Table 17 are not currently supported for this device.
Table 17.
Addr.
(Hex)
Register
Name
Chip configuration registers
0x00
SPI port
configuration
(global)
(MSB)
Bit 7
0
Bit 6 Bit 5
LSB Soft reset
first
Bit 4
1
Bit 3 Bit 2
1
Soft
reset
Bit 1
(LSB)
Bit 0
LSB first 0
0x01 Chip ID (global)
8-bit chip ID, Bits[7:0]
AD9269 = 0x75
0x02 Chip grade (global) Open
Device index and transfer registers
0x05 Channel index
Open
Speed grade ID, Bits[6:4]
20 MSPS = 000
40 MSPS = 001
65 MSPS = 010
80 MSPS = 011
Open Open
Open
Open
Open Open
ADC B ADC A
default default
0xFF Transfer
Open
Open Open
Open
Open Open Open Transfer
Program registers (may or may not be indexed by device index)
0x08 Modes
External
power-
down
enable
(local)
External pin function
0x00 =
full power-down
0x01 = standby
(local)
Open
0x09 Clock (global)
Open
Open Open
0x0B
Clock divider
(global)
Open
Open
Open
00 = chip run
01 = full power-
down
10 = standby
11 = chip-wide
digital reset
(local)
Open
Duty
cycle
stabilize
Clock divider, Bits[2:0]
Clock divide ratio
000 = divide by 1
001 = divide by 2
010 = divide by 3
011 = divide by 4
100 = divide by 5
101 = divide by 6
Default
Value
(Hex)
0x18
0x75
N/A
0x03
0x00
0x80
0x00
0x00
Comments
The nibbles are
mirrored so that
LSB- or MSB-first
mode registers
correctly, regard-
less of shift mode
Unique chip ID
used to differ-
entiate devices;
read only
Unique speed
grade ID used to
differentiate
devices; read
only
Bits are set to
determine which
device on chip
receives the next
write command;
the default is all
devices on chip
Synchronously
transfers data
from the master
shift register to
the slave
Determines
various generic
modes of chip
operation
The divide ratio is
the value plus 1
Rev. 0 | Page 32 of 40
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