AD8052AR-REEL Просмотр технического описания (PDF) - Analog Devices
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AD8052AR-REEL Datasheet PDF : 24 Pages
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AD8051/AD8052/AD8054
ANALOG-TO-DIGITAL AND DIGITAL-TO-ANALOG
APPLICATIONS
Figure 50 is a schematic showing the AD8051 used as a driver
for an AD9201, a 10-bit, 20 MSPS, dual analog-to-digital
converter. This converter is designed to convert I and Q signals in
communications systems. In this application, only the I channel
is being driven. The I channel is enabled by applying a logic
high to SELECT (Pin 13).
The AD8051 is running from a dual supply and is configured
for a gain of +2. The input signal is terminated in 50 Ω and the
output is 2 V p-p, which is the maximum input range of the
AD9201. The 22 Ω series resistor limits the maximum current
that flows and helps to lower the distortion of the ADC.
The AD9201 has differential inputs for each channel. These are
designated the A and B inputs. The B inputs of each channel are
connected to VREF (Pin 22), which supplies a positive reference
of 2.5 V. Each of the B inputs has a small low-pass filter that also
helps to reduce distortion.
The output of the op amp is ac-coupled into INA-I (Pin 16) via
two parallel capacitors to provide good high frequency and low
frequency coupling. The 1 kΩ resistor references the signal to
VREF that is applied to INB-I. Thus, INA-I swings both positive
and negative with respect to the bias voltage applied to INB-I.
With the sampling clock running at 20 MSPS, the analog-to-
digital output was analyzed with a digital analyzer. Two input
frequencies were used, 1 MHz and 9.5 MHz, which is just short
of the Nyquist frequency. These signals were well filtered to
minimize any harmonics.
Figure 48 shows the FFT response of the ADC for the case of a
1 MHz analog input. The SFDR is 71.66 dB, and the analog-to-
digital is producing 8.8 ENOB (effective number of bits). When
the analog frequency was raised to 9.5 MHz, the SFDR was
reduced to −60.18 dB and the ADC operated with 8.46 ENOBs
as shown in Figure 49. The inclusion of the AD8051 in the
circuit did not worsen the distortion performance of the AD9201.
10
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
FUND
2ND 3RD 4TH
7TH
5TH 6TH
12 3 45 67
FREQUENCY (MHz)
8TH 9TH
89
PART# 0
FFTSIZE 8192
FCLK 20.0MHz
FUND 998.5kHz
VIN –0.51dB
THD –68.13
SNR 54.97
SINAD 54.76
ENOB 8.80
SFDR 71.66
2ND –74.53
3RD –76.06
4TH –76.35
5TH –79.05
6TH –80.36
7TH –75.08
8TH –88.12
9TH –77.87
10
Figure 48. FFT Plot for AD8051 Driving the AD9201 at 1 MHz
10
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
2ND
4TH 6TH 8TH
FUND PART# 0
FFTSIZE 8192
FCLK 20.0MHz
FUND 9.5MHz
VIN –0.44dB
THD –57.08
SNR 54.65
SINAD 52.69
ENOB 8.46
3RD
SFDR 60.18
2ND –60.18
7TH 5TH
3RD –60.23
4TH –82.01
5TH –78.83
6TH –81.28
7TH –77.28
8TH –84.54
9TH –92.78
1 2 3 4 5 6 7 8 9 10
FREQUENCY (MHz)
Figure 49. FFT Plot for AD8051 Driving the AD9201 at 9.5 MHz
0.33µF
+5V
0.1µF 10µF
0.01µF
7
3
22Ω
50Ω
AD8051 6
2
4
1kΩ
0.1µF 10µF
–5V
1kΩ
15 SLEEP
CLOCK 14
22Ω
16 INA-I
SELECT 13
1kΩ
22Ω
10pF
17 INB-I
10pF
AD9201
0.1µF 10µF
0.1µF
10µF
0.1µF
18 REFT-I
0.1µF
19 REFB-I
20 AVSS
21 REFSENSE
22 VREF
+5V
23 AVDD
10µF
0.1µF
0.1µF 10µF
0.1µF
24 REFB-Q
0.1µF
25 REFT-Q
22Ω
22Ω
26 INB-Q
10pF
10pF
27 INA-Q
28 CHIP–SELECT
D9 12
D8 11
D7 10
D6 9
D5 8
D4 7
D3 6
D2 5
D1 4
D0 3
DVDD 2
DVSS 1
Figure 50. The AD8051 Driving an AD9201, a 10-Bit, 20 MSPS Analog-to-Digital Converter
Rev. H | Page 19 of 24
+VDD
DATA OUT
0.1µF
+5V
10µF
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