AD7997BRUZ-0 Просмотр технического описания (PDF) - Analog Devices
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AD7997BRUZ-0
Analog Devices
AD7997BRUZ-0 Datasheet PDF : 32 Pages
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AD7997/AD7998
I2C TIMING SPECIFICATIONS
Guaranteed by initial characterization. All values measured with input filtering enabled. CB refers to capacitive load on the bus line. tr and
tf measured between 0.3 VDD and 0.7 VDD.
High speed mode timing specifications apply to the AD7997-1/AD7998-1 only. Standard and fast mode timing specifications apply to
both the AD7997-0/AD7998-0 and the AD7997-1/AD7998-1. See Figure 2. Unless otherwise noted, VDD = 2.7 V to 5.5 V; REFIN = 2.5 V;
TA =TMIN to TMAX.
Table 3.
Parameter
fSCL
t1
t2
t3
t41
t5
t6
t7
t8
t9
Conditions
Standard mode
Fast mode
High speed mode
CB = 100 pF max
CB = 400 pF max
Standard mode
Fast mode
High speed mode
CB = 100 pF max
CB = 400 pF max
Standard mode
Fast mode
High speed mode
CB = 100 pF max
CB = 400 pF max
Standard mode
Fast mode
High speed mode
Standard mode
Fast mode
High speed mode
CB = 100 pF max
CB = 400 pF max
Standard mode
Fast mode
High speed mode
Standard mode
Fast mode
High speed mode
Standard mode
Fast mode
Standard mode
Fast mode
High speed mode
Standard mode
Fast mode
High speed mode
CB = 100 pF max
CB = 400 pF max
AD7997/AD7998 Limit at TMIN, TMAX
Min
Max
Unit
100
kHz
400
kHz
3.4
MHz
1.7
MHz
4
µs
0.6
µs
60
ns
120
ns
4.7
µs
1.3
µs
160
ns
320
ns
250
ns
100
ns
10
ns
0
3.45
µs
0
0.9
µs
0
702
ns
0
150
ns
4.7
µs
0.6
µs
160
ns
4
µs
0.6
µs
160
ns
4.7
µs
1.3
µs
4
µs
0.6
µs
160
ns
1000
ns
20 + 0.1 CB 300
ns
10
80
ns
20
160
ns
Description
Serial clock frequency
tHIGH, SCL high time
tLOW, SCL low time
tSU;DAT, data setup time
tHD;DAT, data hold time
tSU;STA, setup time for a repeated start condition
tHD;STA, hold time (repeated) start condition
tBUF, bus free time between a stop and a start condition
tSU;STO, setup time for stop condition
tRDA, rise time of SDA signal
Rev. 0 | Page 7 of 32
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