AD7993(RevPrF) Просмотр технического описания (PDF) - Analog Devices

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AD7993
(Rev.:RevPrF)

4-Channel, 12-/10-Bit ADCs with I2C Compatible Interface in 16-Lead TSSOP

Analog Devices 

PRELIMINARY TECHNICAL DATA

AD7994/AD7993

1

9

1

9

SCL

SDA

0

START BY

MASTER

1

0 A3 A2 A1 A0 R/9

D7

FRAME 1

SERIAL BUS ADDRESS BYTE

ACK. BY

AD7994/3

D6 D5 D4 D3 D2 D1 D0

NO ACK. BY STOP BY

MASTER MASTER

FRAME 2

SINGLE DATA BYTE FROM AD7994/3

1

SCL

Figure 13. Reading a single byte of data from a selected

register

9

1

9

SDA

0

START BY

MASTER

1

0 A3 A2 A1 A0 R/9

Alert_

Flag

ACK. BY

AD7994/3

FRAME 1

SERIAL BUS ADDRESS BYTE

1

SCL (CONTINUED)

0

D11 D10 D9 D8

CH ID1 CH ID0

FRAME 2

MOST SIGNIFICANT DATA BYTE FROM

AD7994/3

ACK. BY

MASTER

9

SDA (CONTINUED)

D7 D6 D5 D4 D3 D2 D1/0 D0/0

NO ACK. BY STOP BY

MASTER MASTER

FRAME 3

LEAST SIGNIFICANT DATA BYTE FROM

AD7994/3

Figure 14. Reading two bytes of data from the Conversion

Result Register

ALERT/BUSY PIN

The ALERT/BUSY may be configured as an Alert or

Busy ouput as shown in Table VI.

SMBus ALERT

The AD7994/AD7993 ALERT output is an SMBus inter-

rupt line for devices that want to trade their ability to

master for an extra pin. The AD7994/AD7993 is a slave

only device and uses the SMBus ALERT to signal the

host device that it wants to talk. The SMBus ALERT on

the AD7994/AD7993 is used as an out of conversion

range indicator (a limit violation indicator).

The ALERT pin has an open-drain configuration which

allows the ALERT outputs of several AD7994/AD7993

devices to be wired-AND together when the ALERT pin

is active low. D0 of the Configuration Register is used to

set the active polarity of the ALERT output. The power-

up default is active low. The ALERT function can be

disabled or enabled by setting D2 of the Configuration

Register to 1 or 0 respectively.

The host device can process the ALERT interrupt and

simultaneously access all SMBus ALERT devices through

the alert response address. Only the device which pulled

the ALERT low will acknowledge the ARA (Alert Re-

sponse Address). If more than one device pulls the

ALERT pin low, the highest priority (lowest address)

device will win communication rights via standard I2C

arbitration during the slave address transfer.

The ALERT output becomes active when the value in the

Conversion Result Register exceeds the value in the

DATAHIGH Register or falls below the value in the

DATALOW Register . It is reset when a write operation to

the Configuration register sets D1 to a 1, or when the

conversion result returns N LSBs below or above the value

stored in the DATAHIGH Register or DATALOW Register

respectively. N is the value in the Hysteresis register. (See

Limit Registers section)

The ALERT output requires an external pull-up resistor.

This can be connected to a voltage different from VDD

provided the maximum voltage rating of the ALERT out-

put pin is not exceeded. The value of the pull-up resistor

depends on the application, but should be as large as pos-

sible to avoid excessive sink currents at the ALERT out-

put.

REV. PrF

–23–

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