AD7879 Просмотр технического описания (PDF) - Analog Devices
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AD7879 Datasheet PDF : 40 Pages
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AD7879/AD7889
Data Sheet
START
AD7879-1/AD7889-1 DEVICE ADDRESS
SDA
DEV
A6
DEV
A5
DEV
A4
DEV
A3
DEV DEV
A2 A1
DEV
A0
R/W
ACK
SCL
t1
t3
1
2
3
45
6
7
8
9
t2
REGISTER ADDRESS[A7:A0]
A7 A6
A1 A0
10
11
16 17
REGISTER DATA[D15:D8]
REGISTER DATA[D7:D0]
ACK D15 D14
D9 D8 ACK D7 D6
D1 D0 ACK
STOP
START
t8
t4
t5
t6
t7
18 19 20
25 26 27 28 29
34 35 36 37
AD7879-1/AD7889-1
DEVICE ADDRESS
DEV DEV DEV
A6 A5 A4
1
2
3
NOTES
1. A START CONDITION AT THE BEGINNING IS DEFINED AS A HIGH-TO-LOW TRANSITION ON SDA WHILE SCL REMAINS HIGH.
2. A STOP CONDITION AT THE END IS DEFINED AS A LOW-TO-HIGH TRANSITION ON SDA WHILE SCL REMAINS HIGH.
3. 7-BIT DEVICE ADDRESS [DEV A6:DEV A0] = [01011XX], WHERE THE Xs ARE DON'T CARE BITS.
4. REGISTER DATA [D15:D8] AND REGISTER DATA [D7:D0] ARE ALWAYS SEPARATED BY A LOW ACK BIT.
Figure 43. Example of I2C Timing for Single Register Write Operation
Writing Data over the I2C Bus
Reading Data over the I2C Bus
The process of writing to the AD7879-1/AD7889-1 over the I2C
bus is shown in Figure 43 and Figure 45. The device address is
sent over the bus followed by the R/W bit set to 0. This is followed
by one byte of data that contains the 8-bit address of the internal
data register to be written. The bit map in Table 26 shows the
register address byte.
Table 26. I2C Register Address Byte
MSB
LSB
7
6
5
4
3
2
1
0
Register Address
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
The third data byte contains the eight MSBs of the data to be
written to the internal register. The fourth data byte contains
the eight LSBs of data to be written to the internal register.
The AD7879-1/AD7889-1 address pointer register automatically
increments after each write. This allows the master to sequentially
write to all registers on the AD7879-1/AD7889-1 in the same
write transaction. However, the address pointer register does
not wrap after the last address.
To read from the AD7879-1/AD7889-1, the address pointer
register must first be set to the address of the required internal
register. The master performs a write transaction and writes to the
AD7879-1/AD7889-1 to set the address pointer. The master then
outputs a repeat start condition to keep control of the bus or, if
this is not possible, the master ends the write transaction with a
stop condition. A read transaction is initiated, with the R/W bit
set to 1.
The AD7879-1/AD7889-1 supply the upper eight bits of data
from the addressed register in the first readback byte, followed
by the lower eight bits in the next byte. This is shown in Figure 44
and Figure 45.
Because the address pointer automatically increments after each
read, the AD7879-1/AD7889-1 continue to output readback data
until the master puts a no acknowledge and a stop condition on
the bus. If the address pointer reaches its maximum value and the
master continues to read from the device, the AD7879-1/
AD7889-1 repeatedly send data from the last register addressed.
Any data written to the AD7879-1/AD7889-1 after the address
pointer has reached its maximum value is discarded.
All registers on the AD7879-1/AD7889-1 have 16 bits. Two
consecutive 8-bit data bytes are combined and written to the
16-bit registers. To avoid errors, all writes to the device must
contain an even number of data bytes.
To end the transaction, the master generates a stop condition on
SDA, or it generates a repeat start condition if the master is to
maintain control of the bus.
Rev. D | Page 36 of 40
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