AD7765(Rev0) Просмотр технического описания (PDF) - Analog Devices

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AD7765
(Rev.:Rev0)

24-Bit, 156 kSPS, 112 dB Σ-Δ ADC with On-Chip Buffers and Serial Interface

Analog Devices 

PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS

AD7765

VINA– 1

VOUTA+ 2

VINA+ 3

VOUTA– 4

VIN– 5

VIN+ 6

AVDD2 7

AGND3 8

OVERRANGE 9

SCO 10

FSO 11

SDO 12

SDI 13

FSI 14

AD7765

TOP VIEW

(Not to Scale)

28 AVDD3

27 VREF+

26 REFGND

25 AVDD4

24 AVDD1

23 AGND1

22 RBIAS

21 AVDD2

20 AGND2

19 MCLK

18 DEC_RATE

17 DVDD

16 RESET/PWRDWN

15 SYNC

Figure 5. 28-Lead TSSOP Pin Configuration

Table 5. Pin Function Descriptions

Pin No. Mnemonic Description

24

AVDD1

2.5 V Power Supply for Modulator. This pin should be decoupled to AGND1 (Pin 23) with a 100 nF capacitor.

7 and 21 AVDD2

5 V Power Supply. Pin 7 should be decoupled to AGND3 (Pin 8) with a 100 nF capacitor. Pin 21 should be

decoupled to AGND1 (Pin 23) with a 100 nF capacitor.

28

AVDD3

3.3 V to 5 V Power Supply for Differential Amplifier. This pin should be decoupled to the ground plane with a

100 nF capacitor.

25

AVDD4

3.3 V to 5 V Power Supply for Reference Buffer. This pin should be decoupled to AGND1 (Pin 23) with a 100 nF

capacitor.

17

DVDD

2.5 V Power Supply for Digital Circuitry and FIR Filter. This pin should be decoupled to the ground plane with

a 100 nF capacitor.

22

RBIAS

Bias Current Setting Pin. A resistor must be inserted between this pin and AGND. For more details, see the

Bias Resistor Selection section.

23

AGND1

Power Supply Ground for Analog Circuitry.

20

AGND2

Power Supply Ground for Analog Circuitry.

8

AGND3

Power Supply Ground for Analog Circuitry.

26

REFGND

Reference Ground. Ground connection for the reference voltage.

27

VREF+

Reference Input.

1

VINA−

Negative Input to Differential Amplifier.

2

VOUTA+

Positive Output from Differential Amplifier.

3

VINA+

Positive Input to Differential Amplifier.

4

VOUTA−

Negative Output from Differential Amplifier.

5

VIN−

Negative Input to the Modulator.

6

VIN+

Positive Input to the Modulator.

9

OVERRANGE Overrange Pin. This pin outputs a logic high to indicate that the user has applied an analog input that is

approaching the limit of the analog input to the modulator.

10

SCO

Serial Clock Out. This clock signal is derived from the internal ICLK signal. The frequency of this clock is equal

to ICLK. See the Clocking the AD7765 section for further details.

11

FSO

Frame Sync Out. This signal frames the serial data output and is 32 SCO periods wide.

12

SDO

Serial Data Out. Data and status are output on this pin during each serial transfer. Each bit is clocked out on an

SCO rising edge and is valid on the falling edge. See the AD7765 Interface section for further details.

13

SDI

Serial Data In. The first data bit (MSB) must be valid on the next SCO falling edge after the FSI event is latched.

32 bits are required for each write; the first 16-bit word contains the device and register address and the

second word contains the data. See the AD7765 Interface section for further details.

Rev. 0 | Page 9 of 32

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