AD7747 Просмотр технического описания (PDF) - Analog Devices
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AD7747 Datasheet PDF : 28 Pages
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CIN(+)
CAPDAC(+)
17pF
CAPDIFF = 1
CIN(–)
0x000000
TO
0xFFFFFF
±8pF
CDC
DATA
CX
9 TO 25pF
(17pF ± 8pF)
CY
17pF
CAPDAC(–)
17pF
SHLD
Figure 32. Using CAPDAC in Differential Configuration
PARASITIC CAPACITANCE
The CDC architecture used in the AD7747 measures the
capacitance CX connected between the CIN pin and ground.
Most applications use the active shield to avoid external influ-
ences during the CDC. However, any parasitic capacitance, CP,
as shown in Figure 33, can affect the CDC result.
CP1
CX
CP2
CIN
CP3
CDC
DATA
SHLD
Figure 33. Parasitic Capacitance
A parasitic capacitance, CP1, coupled in between CIN and
ground adds directly to the value of the capacitance CX and,
therefore, the CDC result is: DATA ≈ CX + CP1. An offset cali-
bration might be sufficient to compensate for a small parasitic
capacitance (CP1 ≤ 1pF). For a larger parasitic capacitance, the
CAPDAC can be used to compensate, followed by an offset
calibration to ensure the full range of ±8pF is available for
the system.
Other parasitic capacitances, such as CP2 between active shield
and ground as well as CP3 between the CIN pin and SHLD,
could influence the conversion result. However, the graphs in
the Typical Performance Characteristics section show that the
effect of parasitic capacitance of type CP2/CP3 below 250 pF is
insignificant to the CDC result. Figure 7 and Figure 8 show the
gain error caused by CP2. Figure 9 shows the gain error caused
by CP3.
PARASITIC RESISTANCE
RP1
CX
RP2
CIN
RP3
CDC
DATA
SHLD
Figure 34. Parasitic Resistance on CIN
AD7747
Parasitic resistances, as shown in Figure 34, cause leakage
currents, which affect the CDC result. The AD7747 CDC
measures the charge transfer between the CIN pin and ground.
Any resistance connected in parallel to the measured
capacitance, CX, such as the parasitic resistance, RP1, also
transfers charge. Therefore, the parallel resistor is seen as an
additional capacitance in the output data. A resistance in the
range of RP1 ≥ 10 MΩ causes an offset error in the CDC result.
An offset calibration can be used to compensate for the effect of
small leakage currents. A higher leakage current to ground,
RP1 ≤ 10 MΩ, results in a gain error, an offset error, and a
nonlinearity error. See Figure 10 in the Typical Performance
Characteristics section.
A parasitic resistance, R P2, between SHLD and ground, as well
as RP3 between the CIN pin and the active shield, as shown in
Figure 34, cause a leakage current, which affects the CDC result
and is seen as an offset in the data. An offset calibration can be
used to compensate for effect of the small leakage current
caused by a resistance RP2 and RP3 ≥ 200 kΩ. See Figure 11,
Figure 12, and Figure 13 in the Typical Performance
Characteristics section.
PARASITIC SERIAL RESISTANCE
RS
CX
DATA
CIN
CDC
SHLD
Figure 35. Parasitic Serial Resistance
The AD7747 CDC result is affected by a resistance in series
with the measured capacitance. The serial resistance should be
less than 10 kΩ for the specified performance. See Figure 14 in
the Typical Performance Characteristics section.
CAPACITIVE GAIN CALIBRATION
The AD7747 gain is factory calibrated for the full scale of
±8.192 pF in the production for each part individually. The
factory gain coefficient is stored in a one-time programmable
(OTP) memory and is copied to the capacitive gain register at
power-up or after reset.
The gain can be changed by executing a capacitance gain calibra-
tion mode, for which an external full-scale capacitance needs
to be connected to the capacitance input, or by writing a user
value to the capacitive gain register. This change would be only
temporary, and the factory gain coefficient would be reloaded
back after power-up or reset. The part is tested and specified for
use only with the default factory calibration coefficient.
Rev. 0 | Page 23 of 28
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