AD7523 Просмотр технического описания (PDF) - Intersil

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AD7523

8-Bit, Multiplying D/A Converters

Intersil 

AD7523, AD7533

Detailed Description

The AD7523 and AD7533 are monolithic multiplying D/A

converters. A highly stable thin film R-2R resistor ladder

network and NMOS SPDT switches form the basis of the

converter circuit, CMOS level shifters permit low power

TTL/CMOS compatible operation. An external voltage or

current reference and an operational amplifier are all that is

required for most voltage output applications.

A simplified equivalent circuit of the DAC is shown in the

Functional Diagram. The NMOS SPDT switches steer the

ladder leg currents between IOUT1 and IOUT2 buses which

must be held at ground potential. This configuration main-

tains a constant current in each ladder leg independent of

the input code.

Converter errors are further reduced by using separate

metal interconnections between the major bits and the out-

puts. Use of high threshold switches reduce offset (leakage)

errors to a negligible level.

The level shifter circuits are comprised of three inverters with

positive feedback from the output of the second to the first,

see Figure 1. This configuration results in TTL/CMOS

compatible operation over the full military temperature

range. With the ladder SPDT switches driven by the level

shifter, each switch is binarily weighted for an ON resistance

proportional to the respective ladder leg current. This

assures a constant voltage drop across each switch,

creating equipotential terminations for the 2R ladder

resistors and high accurate leg currents.

±10V +15V

VREF

DATA

INPUTS

MSB

LSB

15 14

4

16

AD7523/ 1

AD7533

11 3 2

RFEEDBACK

OUT1

OUT2 CR1

GND

R2

-

6

+

VOUT

NOTES:

1. R1 and R2 used only if gain adjustment is required.

2. CF1 protects AD7523 and AD7533 against negative transients.

FIGURE 2. UNIPOLAR BINARY OPERATION

TABLE 1. UNlPOLAR BINARY CODE - AD7523

DIGITAL INPUT

MSB LSB

ANALOG OUTPUT

11111111

– VR E F  22----55---56-- 

10000001

– VR E F  12----25---96-- 

10000000

–VREF12----25---86-- = –V-----R--2---E----F--

01111111

– VR E F  12----25---76-- 

V+

TTL/

CMOS INPUT

13

4

6 TO LADDER

89

2

5

7

IOUT2 IOUT1

FIGURE 1. CMOS SWITCH

Typical Applications

Unipolar Binary Operation - AD7523 (8-Bit DAC)

The circuit configuration for operating the AD7523 in

unipolar mode is shown in Figure 2. With positive and

negative VREF values the circuit is capable of 2-Quadrant

multiplication. The “Digital Input Code/Analog Output Value”

table for unipolar mode is given in Table 1.

00000001

– VR E F  2----51---6-- 

00000000

–VREF2----50---6-- = 0

NOTE:

1. 1 LSB = (2–8)(VREF) = 2----51---6--(VREF) .

Zero Offset Adjustment

1. Connect all digital inputs to GND.

2. Adjust the offset zero adjust trimpot of the output

operational amplifier for 0V ±1mV (Max) at VOUT.

Gain Adjustment

1. Connect all digital inputs to V+.

2. Monitor VOUT for a -VREF (11/28) reading.

3. To increase VOUT, connect a series resistor, R2, (0Ω to

250Ω) in the IOUT1 amplifier feedback loop.

4. To decrease VOUT, connect a series resistor, R1, (0Ω to

250Ω) between the reference voltage and the VREF

terminal.

10-11

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