AD7298(RevPrA) Просмотр технического описания (PDF) - Analog Devices
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AD7298 Datasheet PDF : 18 Pages
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Preliminary Technical Data
Once the TSENSEBUSY signal goes high, the user may provide a
CS falling edge to frame the read of the previous conversion and
program the control register if required, see Figure 14. Once the
previous conversion result has been read, any subsequent CS
falling edges which occur while the TSENSEBUSY signal is high
are internally ignored by the AD7298. If additional CS falling
edges are provided while TSENSEBUSY is high, the AD7298 will
provide an invalid digital output of all 1’s. Alternatively, if CS
remains high while, TSENSEBUSY is high then the DOUT bus will
remain in three-state.
If the user writes to the control register during the first 16 SCLK
cycles following TSENSEBUSY going high, the configuration of the
device for the next conversion, which will be initiated on the
subsequent CS falling edge after TSENSEBUSY goes low, is altered.
If the user configures the part for partial power down in a write
to the control register during the first 16 SCLK cycles following
AD7298
TSENSEBUSY going high, the temperature sensor conversion will
be aborted and the part will enter partial power down on the
16th SCLK falling edge.
It is thus recommended not to write to the control register if the
CS signal will be toggling while TSENSEBUSY is high. Hence, care
should be taken to ensure that the write bit is set to zero during
the temperature conversion phase when CS is toggling.
If an SCLK frequency of more than 10kHz is used, the
temperature conversion will require more than one standard
read cycle to complete. In this case, the user can monitor the
TSENSEBUSY signal to determine when the conversion is
completed and the result is available for reading.
Figure 14. Serial Interface Timing Diagram for the Temperature Sensor Conversion.
Rev. PrA | Page 17 of 18
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