AD5254 Просмотр технического описания (PDF) - Analog Devices
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AD5254 Datasheet PDF : 32 Pages
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I2C INTERFACE DETAIL DESCRIPTION
From Master to Slave
From Slave to Master
AD5253/AD5254
S = start condition
P = stop condition
A = acknowledge (SDA low)
A = not acknowledge (SDA high)
AD1, AD0 = I2C device address bits, must match with the logic states at Pins AD1, AD0
R/W= read enable bit at logic high; write enable bit at logic low
CMD/REG = command enable bit at logic high; register access bit at logic low
EE/RDAC = EEMEM register at logic high; RDAC register at logic low
A4, A3, A2, A1, A0 = RDAC/EEMEM register addresses
S 0 1 0 1 1 A A 0 A CMD/ 0 EE/ A A A A A A
DD
REG
RDAC 4 3 2 1 0
10
DATA
A/ P
A
SLAVE ADDRESS
0 WRITE
INSTRUCTIONS
AND ADDRESS
0 REG
Figure 27. Single Write Mode
(1 BYTE +
ACKNOWLEDGE)
S 0 1 0 1 1 A A 0 A CMD/ 0 EE/ A A A A A A
DD
10
REG
RDAC 4 3 2 1 0
RDAC_N
DATA
A RDAC_N + 1 A/ P
DATA
A
SLAVE ADDRESS
0 WRITE
0 REG
INSTRUCTIONS
AND ADDRESS
Figure 28. Consecutive Write Mode
(N BYTE +
ACKNOWLEDGE)
Table 6. Addresses for Writing Data Byte Contents to RDAC Registers (R/W = 0, CMD/REG = 0, EE/RDAC = 0)
A4
A3
A2
A1
A0
RDAC
Data Byte Description
0
0
0
0
0
RDAC0
6-/8-bit wiper setting (2 MSB of AD5253 are X)
0
0
0
0
1
RDAC1
6-/8-bit wiper setting (2 MSB of AD5253 are X)
0
0
0
1
0
RDAC2
6-/8-bit wiper setting (2 MSB of AD5253 are X)
0
0
0
1
1
RDAC3
6-/8-bit wiper setting (2 MSB of AD5253 are X)
0
0
1
0
0
Reserved
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0
1
1
1
1
Reserved
Rev. B | Page 15 of 32
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