AD1838A Просмотр технического описания (PDF) - Analog Devices
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производитель
AD1838A Datasheet PDF : 24 Pages
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Parameter
TDM256 MODE (Master, 48 kHz and 96 kHz)
tTBD
tFSD
tTABDD
tTDDS
BCLK Delay
FSTDM Delay
ASDATA Delay
DSDATA1 Setup
tTDDH
DSDATA1 Hold
TDM256 MODE (Slave, 48 kHz and 96 kHz)
fAB
BCLK Frequency
tTBCH
BCLK High
tTBCL
tTFS
BCLK Low
FSTDM Setup
tTFH
FSTDM Hold
tTBDD
tTDDS
ASDATA Delay
DSDATA1 Setup
tTDDH
DSDATA1 Hold
TDM512 MODE (Master, 48 kHz)
tTBD
tFSD
tTABDD
tTDDS
BCLK Delay
FSTDM Delay
ASDATA Delay
DSDATA1 Setup
tTDDH
DSDATA1 Hold
TDM512 MODE (Slave, 48 kHz )
fAB
BCLK Frequency
tTBCH
BCLK High
tTBCL
tTFS
BCLK Low
FSTDM Setup
tTFH
FSTDM Hold
tTBDD
tTDDS
ASDATA Delay
DSDATA1 Setup
tTDDH
DSDATA1 Hold
AUXILIARY INTERFACE (48 kHz and 96 kHz)
tAXDS
tAXDH
tDXD
fABP
Slave Mode
AAUXDATA Setup
AAUXDATA Hold
DAUXDATA Delay
AUXBCLK Frequency
tAXBH
tAXBL
tAXLS
tAXLH
Master Mode
AUXBCLK High
AUXBCLK Low
AUXLRCLK Setup
AUXLRCLK Hold
tAUXBCLK
tAUXLRCLK
AUXBCLK Delay
AUXLRCLK Delay
Specifications subject to change without notice.
Min
15
15
256 ϫ fS
17
17
10
10
15
15
15
15
512 ϫ fS
17
17
10
10
15
15
10
10
20
64 ϫ fS
15
15
10
10
20
15
Max
40
5
10
15
40
5
10
15
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MCLK
PD/RST
tMCLK
tMH
tML
tPDR
Figure 1. MCLK and PD/RST Timing
REV. A
–5–
AD1838A
Comments
From MCLK Rising Edge
From BCLK Rising Edge
From BCLK Rising Edge
To BCLK Falling Edge
From BCLK Falling Edge
To BCLK Falling Edge
From BCLK Falling Edge
From BCLK Rising Edge
To BCLK Falling Edge
From BCLK Falling Edge
From MCLK Rising Edge
From BCLK Rising Edge
From BCLK Rising Edge
To BCLK Falling Edge
From BCLK Falling Edge
To BCLK Falling Edge
From BCLK Falling Edge
From BCLK Rising Edge
To BCLK Falling Edge
From BCLK Falling Edge
To AUXBCLK Rising Edge
From AUXBCLK Rising Edge
From AUXBCLK Falling Edge
To AUXBCLK Rising Edge
From AUXBCLK Rising Edge
From MCLK Rising Edge
From AUXBCLK Falling Edge
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