74LVC169 Просмотр технического описания (PDF) - NXP Semiconductors.

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74LVC169

Presettable synchronous 4-bit up/down binary counter

NXP Semiconductors. 

NXP Semiconductors

74LVC169

Presettable synchronous 4-bit up/down binary counter

In order for counting to occur, both pins CEP and CET must be LOW and pin PE must be

HIGH. The pin U/D input determines the direction of the counting. The terminal count

output pin TC output is normally HIGH and goes LOW, provided that pin CET is LOW,

when a counter reaches 15 in the count up mode. The pin TC output state is not a function

of the count-enable parallel (pin CEP) input level. Since pin TC signal is derived by

decoding the flip-flop states, there exists the possibility of decoding spikes on pin TC. For

this reason the use of pin TC as a clock signal is not recommended; see the following

logic equations:

count enable = CEP  CET  PE

count up: TC = Q3  Q2  Q1  Q0  CET  U  D

count down: TC = Q3  Q2  Q1  Q0  CET  U  D

2. Features and benefits

 5 V tolerant inputs for interfacing with 5 V logic

 Wide supply voltage range from 1.2 V to 3.6 V

 CMOS low power consumption

 Direct interface with TTL levels

 Up/down counting

 Two count enable inputs for n-bit cascading

 Built-in look-ahead carry capability

 Presettable for programmable operation

 Complies with JEDEC standard:

 JESD8-7A (1.65 V to 1.95 V)

 JESD8-5A (2.3 V to 2.7 V)

 JESD8-C/JESD36 (2.7 V to 3.6 V)

 ESD protection:

 HBM JESD22-A114F exceeds 2000 V

 MM JESD22-A115-B exceeds 200 V

 CDM JESD22-C101E exceeds 1000 V

 Multiple package options

 Specified from 40 C to +85 C and from 40 C to +125 C

74LVC169

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 6 — 29 November 2012

© NXP B.V. 2012. All rights reserved.

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