74LVC169 Просмотр технического описания (PDF) - Philips Electronics
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74LVC169 Datasheet PDF : 14 Pages
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Philips Semiconductors
Presettable synchronous 4-bit up/down
binary counter
Product specification
74LVC169
AC WAVEFORMS
VM = 1.5 V at VCC w 2.7 V
VM = 0.5 S VCC at VCC < 2.7 V
VOL and VOH are the typical output voltage drop that occur with the output load.
VI
CP INPUT
GND
VOH
Qn, TC OUTPUT
VOL
1/fMAX
VM
tw
tPHL
VM
tPLH
SY00071
Waveform 1. Clock (CP) to outputs (Qn, TC) propagation
delays, the clock pulse width and the maximum clock
frequency.
VI
PE INPUT
GND
VI
CP INPUT
GND
VI
Dn INPUT
GND
VM
tSU
th
VM
tSU
th
VM
tSU
th
tSU
th
The shaded areas indicate when the input is permitted
to change for predictable output performance.
SC00137
Waveform 4. Setup and hold times for the input (Dn) and
parallel enable input (PE).
CET
TC
VM
VM
tPHL
tPLH
VM
VM
SF00792
Waveform 2. Input (CET) to output (TC) propagation delays
and output transition times.
U/D
TC
VM
VM
tPHL
tPLH
VM
VM
SF00793
Waveform 3. Master reset (MR) pulse width, the master reset
to output (Qn, TC) propagation delays and the master reset to
clock (CP) removal times.
VI
CEP, CET
INPUT
GND
VI
CP INPUT
GND
VM
tsu
th
VM
tsu
th
VM
NOTE: The shaded areas indicate when the input is permitted
to change for predictable output performance.
SC00138
Waveform 5. CEP and CET setup and hold times.
TEST CIRCUIT
PULSE
GENERATOR
VI
RT
VCC
D.U.T.
S1
2 * VCC
Open
GND
500Ω
VO
50pF
CL
500Ω
SWITCH POSITION
TEST
S1
tPLH/tPHL
Open
VCC
< 2.7V
2.7–3.6V
VI
VCC
2.7V
SV00903
Waveform 6. Load circuitry for switching times.
1998 May 20
9
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