74LV165D Просмотр технического описания (PDF) - NXP Semiconductors.
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74LV165D Datasheet PDF : 20 Pages
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Nexperia
74LV165
8-bit parallel-in/serial-out shift register
10. Dynamic characteristics
Table 7. Dynamic characteristics
GND (ground = 0 V); for test circuit, see Figure 12
Symbol Parameter
Conditions
tpd
propagation CE, CP to Q7, Q7;
delay
see Figure 7 and Figure 8
VCC = 1.2 V
VCC = 2.0 V
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
VCC = 3.3 V; CL = 15 pF
VCC = 4.5 V to 5.5 V
PL to Q7, Q7; see Figure 8
VCC = 1.2 V
VCC = 2.0 V
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
VCC = 3.3 V; CL = 15 pF
VCC = 4.5 V to 5.5 V
D7 to Q7, Q7; CL = 15 pF;
see Figure 9
VCC = 1.2 V
VCC = 2.0 V
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
VCC = 3.3 V; CL = 15 pF
VCC = 4.5 V to 5.5 V
tW
pulse width
CP input HIGH to LOW;
see Figure 7
VCC = 2.0 V
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
PL input LOW; see Figure 8
VCC = 2.0 V
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
40 C to +85 C
Min Typ[1] Max
[2]
40 C to +125 C Unit
Min
Max
-
115
-
-
-
38
61
-
-
27
43
-
[3]
-
22
36
-
-
18
-
-
[4]
-
15
24
-
-
ns
76 ns
54 ns
45 ns
-
ns
30 ns
-
110
-
-
-
35
56
-
-
24
39
-
[3]
-
20
33
-
-
18
-
-
[4]
-
14
22
-
-
ns
70 ns
49 ns
41 ns
-
ns
27 ns
-
90
-
-
-
28
45
-
-
20
32
-
[3]
-
17
27
-
-
14
-
-
[4]
-
11
18
-
-
ns
56 ns
40 ns
33 ns
-
ns
22 ns
34
10
-
41
25
8
-
30
[3] 20
7
-
24
[4] 15
5
-
18
34
10
-
41
25
8
-
30
[3] 20
7
-
24
[4] 15
5
-
18
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
74LV165
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 9 March 2016
© Nexperia B.V. 2017. All rights reserved
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