74LV165D Просмотр технического описания (PDF) - NXP Semiconductors.
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74LV165D Datasheet PDF : 20 Pages
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Nexperia
74LV165
8-bit parallel-in/serial-out shift register
Table 7. Dynamic characteristics …continued
GND (ground = 0 V); for test circuit, see Figure 12
Symbol Parameter
Conditions
fmax
maximum
frequency
see Figure 7
VCC = 2.0 V
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
VCC = 3.3 V; CL = 15 pF
VCC = 4.5 V to 5.5 V
CPD
power
dissipation
VI = GND to VCC; VCC = 3.3 V
capacitance
40 C to +85 C
Min Typ[1] Max
40 C to +125 C Unit
Min
Max
14
40
-
12
19
60
-
16
[3] 24
65
-
20
-
78
-
-
[4] 36
75
-
30
[5]
-
35
-
-
MHz
-
MHz
-
MHz
-
MHz
-
MHz
pF
[1] Typical values are measured at Tamb = 25 °C.
[2] tpd is the same as tPHL and tPLH.
[3] Typical values are measured at VCC = 3.3 V.
[4] Typical values are measured at VCC = 5.0 V.
[5] CPD is used to determine the dynamic power dissipation PD = CPD VCC2 fi + (CL VCC2 fo) (PD in W), where:
fi = input frequency in MHz;
fo = output frequency in MHz;
(CL VCC2 fo) = sum of outputs;
CL = output load capacitance in pF;
VCC = supply voltage in V.
11. Waveforms
9,
&3&(LQSXW
*1'
92+
4RU4RXWSXW
92/
IPD[
90
W:
W3+/
90
W3/+
DDD
Fig 7.
Measurement points are given in Table 8.
The changing to output assumes that internal Q6 is opposite state from Q7.
Clock pulse (CP) and clock enable (CE) to output (Q7 or Q7) propagation delays, clock pulse width and
maximum clock frequency
74LV165
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 9 March 2016
© Nexperia B.V. 2017. All rights reserved
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