Mode Select Table
Inputs
PL CE U/D CP
Mode
H
L
L
Count Up
H
L
H
Count Down
L
X X X Preset (Asyn.)
H
H X X No Change (Hold)
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW-to-HIGH Clock Transition
= LOW Pulse
RC Truth Table
Inputs
CE
TC(1)
CP
L
H
H
X
X
X
L
X
Note:
1. TC is generated internally.
Output
RC
H
H
Figure 1. n-Stage Counter Using Ripple Clock
Figure 2. Synchronous n-Stage Counter Using Ripple Carry/Borrow
Figure 3. Synchronous n-Stage Counter with Gated Carry/Borrow
©1988 Fairchild Semiconductor Corporation
74F191 Rev. 1.0.2
3
www.fairchildsemi.com