MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Hex Inverter
High–Performance Silicon–Gate CMOS
The MC54/74HC04A is identical in pinout to the LS04 and the
MC14069. The device inputs are compatible with Standard CMOS out-
puts; with pullup resistors, they are compatible with LSTTL outputs.
The device consists of six three–stage inverters.
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS and TTL
• Operating Voltage Range: 2 to 6V
• Low Input Current: 1µA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance With the JEDEC Standard No. 7A Requirements
• Chip Complexity: 36 FETs or 9 Equivalent Gates
LOGIC DIAGRAM
1
A1
2
Y1
3
A2
4
Y2
5
A3
9
A4
6
Y3
Y=A
8
Y4
11
A5
10
Y5
13
A6
12
Y6
MC54/74HC04A
14
1
J SUFFIX
CERAMIC PACKAGE
CASE 632–08
14
1
14
1
N SUFFIX
PLASTIC PACKAGE
CASE 646–06
D SUFFIX
SOIC PACKAGE
CASE 751A–03
14
1
DT SUFFIX
TSSOP PACKAGE
CASE 948G–01
ORDERING INFORMATION
MC54HCXXAJ
MC74HCXXAN
MC74HCXXAD
MC74HCXXADT
Ceramic
Plastic
SOIC
TSSOP
FUNCTION TABLE
Inputs
Outputs
A
Y
L
H
H
L
Pinout: 14–Lead Packages (Top View)
VCC A6 Y6 A5 Y5 A4 Y4
14 13 12 11 10 9 8
1234567
A1 Y1 A2 Y2 A3 Y3 GND
10/95
© Motorola, Inc. 1995
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