28F128 Просмотр технического описания (PDF) - Intel

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28F128

3 Volt Intel® StrataFlash™ Memory

Intel 

28F128J3A, 28F640J3A, 28F320J3A

3.0

Bus Operations

The local CPU reads and writes flash memory in-system. All bus cycles to or from the flash

memory conform to standard microprocessor bus cycles.

Figure 4. Memory Map

A [23-0]:128 Mbit

A [22-0]: 64 Mbit

A [21-0]: 32 Mbit

FFFFFF

FE0000

128-Kbyte Block 127

A [23-1]: 128 Mbit

A [22-1]: 64 Mbit

A [21-1]: 32 Mbit

7FFFFF

7F0000

64-Kword Block 127

7FFFFF

7E0000

128-Kbyte Block 63

3FFFFF

3F0000

64-Kword Block 63

3FFFFF

3E0000

128-Kbyte Block 31

1FFFFF

1F0000

64-Kword Block 31

03FFFF

020000

01FFFF

000000

128-Kbyte Block 1

128-Kbyte Block 0

Byte-Wide (x8) Mode

01FFFF

010000

00FFFF

000000

64-Kword Block 1

64-Kword Block 0

Word Wide (x16) Mode

Table 2. Chip Enable Truth Table

CE2

VIL

VIL

VIL

VIL

VIH

VIH

VIH

VIH

CE1

VIL

VIL

VIH

VIH

VIL

VIL

VIH

VIH

CE0

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

NOTE: For single-chip applications, CE2 and CE1 can be strapped to GND.

DEVICE

Enabled

Disabled

Disabled

Disabled

Enabled

Enabled

Enabled

Disabled

Preliminary

7

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