Data Sheet
AD7276/AD7277/AD7278
t1
CS
SCLK
tCONVERT
t2
t6
1
2
3
4
5
t3
SDATA THREE-
STATE
Z ZERO
2 LEADING
ZEROS
DB11
DB10
t4
DB9
B
13
t7
DB1
DB0
1/THROUGHPUT
14
15
16
t5
ZERO
ZERO
2 TRAILING
ZEROS
t8
tQUIET
THREE-STATE
Figure 32. AD7276 Serial Interface Timing Diagram 16 SCLK Cycle
t1
CS
SCLK
t2
1
2
t3
SDATA THREE-
STATE
Z ZERO
2 LEADING
ZEROS
t4
DB9
tCONVERT
3
4
t5
DB8
10
DB1
B
11
DB0
t6
12
13
14
15
16
t7
t8
tQUIET
ZERO
ZERO ZERO ZERO
4 TRAILING ZEROS
THREE-STATE
1/THROUGHPUT
Figure 33. AD7277 Serial Interface Timing Diagram
CS
SCLK
t2
1
2
SDATA THREE-
STATE
t3
Z ZERO
2 LEADING
ZEROS
t4
DB7
tCONVERT
3
4
t5
DB6
t1
t6
8
DB1
B
9
DB0
10
11
14
15
16
t7
t8
tQUIET
ZERO
ZERO ZERO
6 TRAILING ZEROS
THREE-STATE
1/THROUGHPUT
Figure 34. AD7278 Serial Interface Timing Diagram
CS
SCLK
t2
1
2
SDATA
THREE-
STATE
Z ZERO
DB7
2 LEADING ZEROS
t1
tCONVERT
3
4
t6
5
8.5 (1/fSCLK)
DB6
DB5
B
9
10
t8
tQUIET
tACQ
DB1
DB0
THREE-STATE
1/THROUGHPUT
Figure 35. AD7278 in a 10 SCLK Cycle Serial Interface
Rev. E | Page 23 of 28