AD8318 Просмотр технического описания (PDF) - Analog Devices

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производитель

AD8318

1 MHz to 8 GHz, 70 dB Logarithmic Detector/Controller

Analog Devices 

AD8318

0

1.2

–5

1.0

–10

0.8

–15

0.6

–20

0.4

–25

0.2

–30

0

–35

–0.2

–40

–0.4

–45

–0.6

–50

–0.8

–55

–1.0

–60

–1.2

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

VSET (V)

Figure 44. AD8367 Output Power vs. AD8318 Setpoint Voltage

For the AGC loop to remain locked, the AD8318 must track the

envelope of the VGA output signal and provide the necessary

voltage levels to the AD8367 gain control input. Figure 45

shows an oscilloscope screen image of the AGC loop depicted

in Figure 43. A 50 MHz sine wave with 50% AM modulation is

applied to the AD8367. The output signal from the VGA is a

constant envelope sine wave with an amplitude corresponding

to a setpoint voltage at the AD8318 of 1.0 V.

AM MODULATED INPUT

1

AD8318 VOUT

2

AD8367 OUTPUT

3

CH1 50.0mV CH2 200mV

CH3 20.0mV

M4.00ms A CH2 64.0mV

Figure 45. Oscilloscope Screen Image Showing an AM Modulated

Input Signal to the AD8367. The AD8318 tracks the envelope

of this input signal and applies the appropriate voltage to ensure

a constant output from the AD8367.

The 45 dB control range is constant for the range of VSET

voltages. The input power levels to the AD8367 must be optimized

to achieve this range. In Figure 46, the minimum and maximum

input power levels are shown vs. setpoint voltage.

Data Sheet

10

0

MAXIMUM INPUT LEVEL

–10

–20

–30

–40

MINIMUM INPUT LEVEL

–50

–60

–70

–80

0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5

VSET (V)

Figure 46. Setpoint Voltage vs. Input Power. Optimal

signal levels must be used to achieve the full 45 dB

dynamic range capabilities of the AD8367.

In some cases, if VGAIN is >1.0 V it can take an unusually long

time for the AGC loop to recover; that is, the output of the

AD8318 remains at an abnormally high value and the gain is set

to its maximum level. A voltage divider is placed between the

output of the AD8318 and the AD8367 GAIN pin to ensure that

VGAIN does not exceed 1.0 V.

In Figure 43, CHP and RHP are configured to reduce oscillation

and distortion due to harmonics at higher gain settings. Some

additional filtering is recommended between the output of the

AD8367 and the input of the AD8318. This helps to decrease

the output noise of the AD8367, which can reduce the dynamic

range of the loop at higher gain settings (smaller VSET).

Response time and the amount of signal integration are controlled

by CFLT. This functionality is analogous to the feedback capacitor

around an integrating amplifier. Though it is possible to use

large capacitors for CFLT, in most applications, values under 1 nF

provide sufficient filtering.

Calibration in controller mode is similar to the method used in

measurement mode. Do a simple 2-point calibration by applying

two known VSET voltages or DAC codes and measuring the

output power from the VGA. Slope and intercept are calculated

using Equation 20 to Equation 22:

Slope = (VSET1 − VSET2)/(POUT1 − POUT2)

(20)

Intercept = POUT1 − VSET1/Slope

(21)

VSET = Slope × (Px − Intercept)

(22)

For more information on AGC applications, refer to the

AD8367 data sheet or ADL5330 data sheet.

Rev. D | Page 20 of 24

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