MCP41100-IP Просмотр технического описания (PDF) - Microchip Technology
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MCP41100-IP Datasheet PDF : 32 Pages
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MCP41XXX/42XXX
DC CHARACTERISTICS: 50 kΩ VERSION
Electrical Characteristics: Unless otherwise indicated, VDD = +2.7V to 5.5V, TA = -40°C to +85°C (TSSOP devices are only specified at +25°C and
+85°C). Typical specifications represent values for VDD = 5V, VSS = 0V, VB = 0V, TA = +25°C.
Parameters
Sym
Min
Typ
Max
Units
Conditions
Rheostat Mode
Nominal Resistance
Rheostat Differential Non-Linearity
R
35
50
65
kΩ TA = +25°C (Note 1)
R-DNL
-1
±1/4
+1
LSB Note 2
Rheostat Integral Non-Linearity
R-INL
-1
±1/4
+1
LSB Note 2
Rheostat Tempco
Wiper Resistance
Wiper Current
Nominal Resistance Match
Potentiometer Divider
∆RAB/∆T
—
RW
—
RW
—
IW
-1
∆R/R
—
800
—
ppm/°C
125
175
Ω VDD = 5.5V, IW = 1 mA, code 00h
175
250
Ω VDD = 2.7V, IW = 1 mA, code 00h
—
+1
mA
0.2
1
% MCP42050 only, P0 to P1;TA = +25°C
Resolution
N
8
—
—
Bits
Monotonicity
N
8
—
—
Bits
Differential Non-Linearity
DNL
-1
±1/4
+1
LSB Note 3
Integral Non-Linearity
INL
-1
±1/4
+1
LSB Note 3
Voltage Divider Tempco
Full-Scale Error
Zero-Scale Error
Resistor Terminals
∆VW/∆T
—
1
—
ppm/°C Code 80h
VWFSE
-1
-0.25
0
LSB Code FFh, VDD = 5V, see Figure 2-25
VWFSE
-1
-0.35
0
LSB Code FFh, VDD = 3V, see Figure 2-25
VWZSE
0
+0.25
+1
LSB Code 00h, VDD = 5V, see Figure 2-25
VWZSE
0
+0.35
+1
LSB Code 00h, VDD = 3V, see Figure 2-25
Voltage Range
VA,B,W
0
—
Capacitance (CA or CB)
—
11
Capacitance
CW
—
5.6
Dynamic Characteristics (All dynamic characteristics use VDD = 5V)
Bandwidth -3dB
BW
—
280
VDD
Note 4
—
pF f =1 MHz, Code = 80h, see Figure 2-30
—
pF f =1 MHz, Code = 80h, see Figure 2-30
—
MHz VB = 0V, Measured at Code 80h,
Output Load = 30 PF
Settling Time
tS
—
8
—
µS VA = VDD,VB = 0V, ±1% Error Band, Transition
from Code 00h to Code 80h, Output Load = 30 pF
Resistor Noise Voltage
eNWB
—
20
—
nV/√Hz
Crosstalk
CT
—
-95
—
dB
Digital Inputs/Outputs (CS, SCK, SI, SO) See Figure 2-12 for RS and SHDN pin operation.
VA = Open, Code 80h, f =1 kHz
VA = VDD, VB = 0V (Note 5)
Schmitt Trigger High-Level Input Voltage
Schmitt Trigger Low-Level Input Voltage
Hysteresis of Schmitt Trigger Inputs
Low-Level Output Voltage
High-Level Output Voltage
Input Leakage Current
Pin Capacitance (All inputs/outputs)
Power Requirements
VIH
VIL
VHYS
VOL
VOH
ILI
CIN, COUT
0.7VDD
—
—
—
VDD - 0.5
-1
—
—
—
0.05VDD
—
—
—
10
—
0.3VDD
—
0.40
—
+1
—
V
V
V IOL = 2.1 mA, VDD = 5V
V IOH = -400 µA, VDD = 5V
µA CS = VDD, VIN = VSS or VDD, includes VA SHDN=0
pF VDD = 5.0V, TA = +25°C, fc = 1 MHz
Operating Voltage Range
Supply Current, Active
VDD
IDDA
2.7
—
5.5
V
—
340
500
µA VDD = 5.5V, CS = VSS, fSCK = 10 MHz,
SO = Open, Code FFh (Note 6)
Supply Current, Static
IDDS
—
0.01
1
µA CS, SHDN, RS = VDD = 5.5V, SO = Open (Note 6)
Power Supply Sensitivity
PSS
—
0.0015 0.0035 %/% VDD = 4.5V - 5.5V, VA = 4.5V, Code 80h
PSS
—
0.0015 0.0035 %/% VDD = 2.7V - 3.3V, VA = 2.7V, Code 80h
Note 1:
2:
3:
4:
5:
6:
VAB = VDD, no connection on wiper.
Rheostat position non-linearity R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum
resistance wiper positions. R-DNL measures the relative step change from the ideal between successive tap positions. IW = VDD/R for
+3V or +5V for 50 kΩ version. See Figure 2-26 for test circuit.
INL and DNL are measured at VW with the device configured in the voltage divider or potentiometer mode. VA = VDD and VB = 0V. DNL
specification limits of ±1 LSB max are specified monotonic operating conditions. See Figure 2-25 for test circuit.
Resistor terminals A,B and W have no restrictions on polarity with respect to each other. Full-scale and zero-scale error were measured
using Figure 2-25.
Measured at VW pin where the voltage on the adjacent VW pin is swinging full scale.
Supply current is independent of current through the potentiometers.
2003 Microchip Technology Inc.
DS11195C-page 3
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