CY7C1486BV25-250BGXI Просмотр технического описания (PDF) - Cypress Semiconductor
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CY7C1486BV25-250BGXI Datasheet PDF : 31 Pages
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CY7C1480BV25
CY7C1482BV25, CY7C1486BV25
Maximum Ratings
Exceeding the maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied ............................................ –55°C to +125°C
Supply Voltage on VDD Relative to GND ........–0.3V to +3.6V
Supply Voltage on VDDQ Relative to GND.......–0.3V to +VDD
DC Voltage Applied to Outputs
in Tri-State ........................................... –0.5V to VDDQ + 0.5V
DC Input Voltage ................................... –0.5V to VDD + 0.5V
Current into Outputs (LOW) ........................................ 20 mA
Static Discharge Voltage........................................... >2001V
(MIL-STD-883, Method 3015)
Latch Up Current .................................................... >200 mA
Operating Range
Range
Commercial
Industrial
Ambient
Temperature
0°C to +70°C
–40°C to +85°C
VDD
VDDQ
2.5V –5%/+5% 2.5V–5% to
VDD
Electrical Characteristics
Over the Operating Range[12, 13]
Parameter
Description
Test Conditions
VDD
VDDQ
VOH
VOL
VIH
VIL
IX
Power Supply Voltage
IO Supply Voltage
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage[12]
Input LOW Voltage[12]
Input Leakage Current
except ZZ and MODE
For 2.5V IO
For 2.5V IO, IOH = –1.0 mA
For 2.5V IO, IOL = 1.0 mA
For 2.5V IO
For 2.5V IO
GND ≤ VI ≤ VDDQ
IOZ
IDD[14]
Input Current of MODE
Input Current of ZZ
Output Leakage Current
VDD Operating Supply
Current
Input = VSS
Input = VDD
Input = VSS
Input = VDD
GND ≤ VI ≤ VDDQ, Output Disabled
VDD = Max, IOUT = 0 mA,
f = fMAX = 1/tCYC
4.0-ns cycle, 250 MHz
5.0-ns cycle, 200 MHz
6.0-ns cycle, 167 MHz
ISB1
Automatic CE
VDD = Max, Device Deselected, 4.0-ns cycle, 250 MHz
Power Down
VIN ≥ VIH or VIN ≤ VIL
5.0-ns cycle, 200 MHz
Current—TTL Inputs
f = fMAX = 1/tCYC
6.0-ns cycle, 167 MHz
ISB2
Automatic CE
VDD = Max, Device Deselected, All speeds
Power Down
VIN ≤ 0.3V or VIN > VDDQ – 0.3V,
Current—CMOS Inputs f = 0
ISB3
Automatic CE
VDD = Max, Device Deselected, or 4.0-ns cycle, 250 MHz
Power Down
VIN ≤ 0.3V or VIN > VDDQ – 0.3V 5.0-ns cycle, 200 MHz
Current—CMOS Inputs f = fMAX = 1/tCYC
6.0-ns cycle, 167 MHz
ISB4
Automatic CE
VDD = Max, Device Deselected, All speeds
Power Down
VIN ≥ VIH or VIN ≤ VIL, f = 0
Current—TTL Inputs
Min
2.375
2.375
2.0
1.7
–0.3
–5
–30
–5
–5
Max
2.625
VDD
0.4
VDD + 0.3V
0.7
5
5
30
5
450
450
400
200
200
200
120
200
200
200
135
Unit
V
V
V
V
V
V
μA
μA
μA
μA
μA
μA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Notes
12. Overshoot: VIH(AC) < VDD +1.5V (pulse width less than tCYC/2).Undershoot: VIL(AC) > –2V (pulse width less than tCYC/2).
13. Power up: assumes a linear ramp from 0V to VDD(min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
14. The operation current is calculated with 50% read cycle and 50% write cycle.
Document #: 001-15143 Rev. *D
Page 19 of 31
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