MT48LC16M16A2BG-6A Просмотр технического описания (PDF) - Micron Technology

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MT48LC16M16A2BG-6A

256Mb: x4, x8, x16 SDRAM

Micron Technology 

256Mb: x4, x8, x16 SDRAM

Clock Suspend

Clock Suspend

The clock suspend mode occurs when a column access/burst is in progress and CKE is

registered LOW. In the clock suspend mode, the internal clock is deactivated, freezing

the synchronous logic.

For each positive clock edge on which CKE is sampled LOW, the next internal positive

clock edge is suspended. Any command or data present on the input balls when an in-

ternal clock edge is suspended will be ignored; any data present on the DQ balls re-

mains driven; and burst counters are not incremented, as long as the clock is suspen-

ded.

Exit clock suspend mode by registering CKE HIGH; the internal clock and related opera-

tion will resume on the subsequent positive clock edge.

Figure 55: Clock Suspend During WRITE Burst

T0

T1

T2

T3

CLK

T4

T5

CKE

Internal

clock

Command

NOP

WRITE

NOP

NOP

Address

Bank,

Col n

DIN

DIN

DIN

DIN

Don’t Care

Note: 1. For this example, BL = 4 or greater, and DQM is LOW.

PDF: 09005aef8091e6d1

256Mb_sdr.pdf - Rev. S 12/12 EN

84

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