MT48LC16M16A2F4-7E Просмотр технического описания (PDF) - Micron Technology

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MT48LC16M16A2F4-7E

256Mb: x4, x8, x16 SDRAM

Micron Technology 

256Mb: x4, x8, x16 SDRAM

PRECHARGE Operation

Figure 49: WRITE Without Auto Precharge

T0

T1

T2

T3

CLK

tCK

tCKS tCKH

tCL

tCH

CKE

tCMS tCMH

Command

ACTIVE

NOP

WRITE

NOP

DQM

tCMS tCMH

Address

A10

BA0, BA1

tAS tAH

Row

tAS tAH

Row

tAS tAH

Bank

Column m

Disable auto precharge

Bank

DQ

tRCD

tRAS

tRC

tDS tDH

DIN

tDS tDH

DIN

T4

NOP

tDS tDH

DIN

T5

NOP

tDS tDH

DIN

T6

NOP

tWR

T7

PRECHARGE

All banks

Single bank

Bank

T8

NOP

tRP

T9

ACTIVE

Row

Row

Bank

Don’t Care

Note: 1. For this example, BL = 4 and the WRITE burst is followed by a manual PRECHARGE.

PDF: 09005aef8091e6d1

256Mb_sdr.pdf - Rev. S 12/12 EN

76

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© 1999 Micron Technology, Inc. All rights reserved.

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