MT48LC16M16A2F4-7E Просмотр технического описания (PDF) - Micron Technology

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MT48LC16M16A2F4-7E

256Mb: x4, x8, x16 SDRAM

Micron Technology 

256Mb: x4, x8, x16 SDRAM

PRECHARGE Operation

Figure 43: READ Without Auto Precharge

T0

CLK

T1

tCK

tCKS tCKH

CKE

tCMS tCMH

Command

ACTIVE

NOP

DQM

tAS tAH

T2

tCL

tCH

READ

tCMS tCMH

Address

Row

Column m

A10

BA0, BA1

tAS tAH

Row

tAS tAH

Bank

Disable auto precharge

Bank

T3

NOP

DQ

tRCD

tRAS

tRC

CL = 2

tAC

tLZ

T4

NOP

tAC

tOH

DOUT

T5

T6

T7

NOP

PRECHARGE

NOP

tAC

tOH

DOUT

All banks

Single bank

Bank(s)

tAC

tOH

DOUT

tRP

tOH

DOUT

tHZ

T8

ACTIVE

Row

Row

Bank

Don’t Care

Undefined

Note: 1. For this example, BL = 4, CL = 2, and the READ burst is followed by a manual PRE-

CHARGE.

PDF: 09005aef8091e6d1

256Mb_sdr.pdf - Rev. S 12/12 EN

71

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© 1999 Micron Technology, Inc. All rights reserved.

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