MT47H128M8SH-187EITM Просмотр технического описания (PDF) - Micron Technology

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MT47H128M8SH-187EITM

1Gb: x4, x8, x16 DDR2 SDRAM

Micron Technology 

1Gb: x4, x8, x16 DDR2 SDRAM

WRITE

Figure 63: WRITE-to-PRECHARGE

CK#

CK

Command

T0

WRITE

Address

Bank a,

Col b

tDQSS (NOM)

DQS#

DQS

DQ

DM

tDQSS (MIN)

DQS#

DQS

DQ

DM

tDQSS (MAX)

DQS#

DQS

DQ

DM

T1

T2

T2n

T3 T3n

T4

NOP

NOP

NOP

NOP

WL + tDQSS

1

DI

b

WL - tDQSS

1

DI

b

WL + tDQSS

1

DI

b

T5

T6

NOP

NOP

tWR

T7

PRE

tRP

(aBoarnka,ll)

Transitioning Data

Don’t Care

Notes:

1. Subsequent rising DQS signals must align to the clock within tDQSS.

2. DI b = data-in for column b.

3. Three subsequent elements of data-in are applied in the programmed order following

DI b.

4. BL = 4, CL = 3, AL = 0; thus, WL = 2.

5. tWR is referenced from the first positive CK edge after the last data-in pair.

6. The PRECHARGE and WRITE commands are to the same bank. However, the PRECHARGE

and WRITE commands may be to different banks, in which case tWR is not required and

the PRECHARGE command could be applied earlier.

7. A10 is LOW with the WRITE command (auto precharge is disabled).

PDF: 09005aef8565148a

1GbDDR2.pdf – Rev. AA 07/14 EN

109

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© 2007 Micron Technology, Inc. All rights reserved.

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