MT47H128M8SH-187EITM Просмотр технического описания (PDF) - Micron Technology

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MT47H128M8SH-187EITM

1Gb: x4, x8, x16 DDR2 SDRAM

Micron Technology 

1Gb: x4, x8, x16 DDR2 SDRAM

WRITE

Figure 58: Write Burst

CK#

CK

Command

Address

tDQSS (NOM)

DQS, DQS#

DQ

DM

tDQSS (MIN)

DQS, DQS#

DQ

DM

T0

WRITE

Bank a,

Col b

tDQSS (MAX)

DQS, DQS#

DQ

DM

T1

T2

T2n T3

T3n T4

NOP

NOP

WL ± tDQSS

DI

b

WL - tDQSS

DI

b

NOP

NOP

5

tDQSS5

WL + tDQSS

DI

b

tDQSS5

Transitioning Data

Don’t Care

Notes:

1. Subsequent rising DQS signals must align to the clock within tDQSS.

2. DI b = data-in for column b.

3. Three subsequent elements of data-in are applied in the programmed order following

DI b.

4. Shown with BL = 4, AL = 0, CL = 3; thus, WL = 2.

5. A10 is LOW with the WRITE command (auto precharge is disabled).

PDF: 09005aef8565148a

1GbDDR2.pdf – Rev. AA 07/14 EN

105

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