M48Z2M1PL Просмотр технического описания (PDF) - STMicroelectronics
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M48Z2M1PL Datasheet PDF : 17 Pages
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M48Z2M1, M48Z2M1Y
Data Retention Mode
With valid VCC applied, the M48Z2M1/Y operates
as a conventional BYTEWIDE™ static RAM.
Should the supply voltage decay, the RAM will au-
tomatically power-fail deselect, write protecting it-
self tWP after VCC falls below VPFD. All outputs
become high impedance, and all inputs are treated
as “Don't care.”
If power fail detection occurs during a valid ac-
cess, the memory cycle continues to completion. If
the memory cycle fails to terminate within the time
tWP, write protection takes place. When VCC drops
below VSO, the control circuit switches power to
the internal energy source which preserves data.
The internal coin cells will maintain data in the
M48Z2M1/Y after the initial application of VCC for
an accumulated period of at least 10 years when
VCC is less than VSO. As system power returns
and VCC rises above VSO, the batteries are dis-
connected, and the power supply is switched to
external VCC. Write protection continues for tER af-
ter VCC reaches VPFD to allow for processor stabi-
lization. After tER, normal RAM operation can
resume.
For more information on Battery Storage life refer
to the Application Note AN1012.
Figure 10. Power Down/Up Mode AC Waveforms
VCC
VPFD (max)
VPFD (min)
VSO
tF
tFB
tWP
E
RECOGNIZED
tDR
tRB
DON'T CARE
tR
tER
RECOGNIZED
OUTPUTS
VALID
(PER CONTROL INPUT)
HIGH-Z
VALID
(PER CONTROL INPUT)
AI01031
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