10-Bit, 22Msps, Full-Duplex
Analog Front-End
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 22MHz (50% duty cycle), Rx ADC input
amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, CM1 = 0, CM0 = 0, differential Rx ADC input, differential Tx DAC output,
CREFP = CREFN = CCOM = 0.33µF, CL < 5pF on all aux-DAC outputs, TA = TMIN to TMAX, unless otherwise noted. Typical values are
at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
SERIAL-INTERFACE TIMING CHARACTERISTICS (Figures 6 and 8, Note 2)
Falling Edge of CS/WAKE to Rising
Edge of First SCLK Time
tCSS
10
DIN to SCLK Setup Time
tDS
10
DIN to SCLK Hold Time
tDH
0
SCLK Pulse-Width High
tCH
25
SCLK Pulse-Width Low
tCL
25
SCLK Period
tCP
50
SCLK to CS/WAKE Setup Time
tCS
10
CS/WAKE High Pulse Width
tCSW
80
CS/WAKE High to DOUT
Active High
tCSD
Bit AD0 set
CS/WAKE High to DOUT Low
(Aux-ADC Conversion Time)
tCONV
Bit AD0 set, no averaging, fCLK = 22MHz,
CLK divider = 8
DOUT Low to CS/WAKE Setup
Time
tDCS Bit AD0, AD10 set
SCLK Low to DOUT Data Out
CS/WAKE High to DOUT High
Impedance
tCD
tCHZ
Bit AD0, AD10 set
Bit AD0, AD10 set
MODE-RECOVERY TIMING CHARACTERISTICS (Figure 7)
Shutdown Wake-Up Time
(With CLK)
tWAKE,SD
From shutdown to Rx mode, ADC settles
to within 1dB SINAD
From shutdown to Tx mode, DAC settles to
within 10 LSB error
From aux-ADC enable to aux-ADC start
conversion
From shutdown to aux-DAC output valid
From shutdown to FD mode, ADC settles
to within 1dB SINAD, DAC settles to within
10 LSB error
TYP MAX UNITS
ns
ns
ns
ns
ns
ns
ns
ns
200
ns
4.3
µs
200
ns
14.5
ns
200
ns
500
26.2
10
µs
28
500
From idle to Rx mode, ADC settles to within
1dB SINAD
7.2
Idle Wake-Up Time
(With CLK)
From idle to Tx mode, DAC settles to 10
tWAKE,ST0 LSB error
5.1
µs
From idle to FD mode, ADC settles to
within 1dB SINAD, DAC settles to within 10
7.2
LSB error
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