MAX1179C Просмотр технического описания (PDF) - Maxim Integrated

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MAX1179C

16-Bit, 135ksps, Single-Supply ADCs with Bipolar Analog Input Range

Maxim Integrated 

16-Bit, 135ksps, Single-Supply ADCs with

Bipolar Analog Input Range

CS

R/C

EOC

D0–D15

tCSL

tDH

HIGH-Z

tCSH

tACQ

REF POWER-

DOWN CONTROL

tDS

tCONV

tDV

tDO

tEOC

tBR

DATA VALID

HIGH-Z

Figure 2. MAX1179/MAX1187/MAX1189 Timing Diagram

+5V ANALOG

0.1µF

ANALOG

INPUT

AVDD

AIN

+5V DIGITAL

0.1µF

DVDD

D0–D15

µP DATA

BUS

16-BIT

WIDE

MAX1179

MAX1187

R/C MAX1189 EOC

CS

REF

RESET

REFADJ

AGND DGND

0.1µF

10µF

Figure 3. Typical Application Circuit for the MAX1179/MAX1187/

MAX1189

Track and Hold (T/H)

In track mode, the internal hold capacitor acquires the

analog signal (see Figure 4). In hold mode, the T/H

switches open and the capacitive DAC samples the

analog input. During the acquisition, the analog input

(AIN) charges capacitor CHOLD. The acquisition ends

on the second falling edge of CS. At this instant, the

T/H switches open. The retained charge on CHOLD rep-

resents a sample of the input. In hold mode, the capac-

itive DAC adjusts during the remainder of the

conversion time to restore node T/H OUT to zero within

the limits of a 16-bit resolution. Force CS low to put

valid data on the bus after conversion is complete.

Power-Down Modes

Select standby mode or shutdown mode with R/C during

the second falling edge of CS (see Selecting Standby or

Shutdown Mode section). The MAX1179/MAX1187/

MAX1189 automatically enter either standby mode (ref-

erence and buffer on) or shutdown (reference and buffer

off) after each conversion depending on the status of

R/C during the second falling edge of CS.

Internal Clock

The MAX1179/MAX1187/MAX1189 generate an internal

conversion clock to free the microprocessor from the bur-

den of running the SAR conversion clock. Total conver-

sion time after entering hold mode (second falling edge of

CS) to end-of-conversion (EOC) falling is 4.7µs (max).

Applications Information

Starting a Conversion

CS and R/C control acquisition and conversion in the

MAX1179/MAX1187/MAX1189 (see Figure 2). The first

falling edge of CS powers up the device and puts it in

acquire mode if R/C is low. The convert start (CS) is

ignored if R/C is high. The MAX1179/MAX1187/

MAX1189 need at least 12ms (CREFADJ = 0.1µF, CREF

= 10µF) for the internal reference to wake up and settle

before starting the conversion, if powering up from

shutdown. Reset the MAX1179/MAX1187/ MAX1189 by

toggling RESET with CS high. The next falling edge of

CS begins acquisition.

Selecting Standby or Shutdown Mode

The MAX1179/MAX1187/MAX1189 have a selectable

standby or low-power shutdown mode. In standby

mode, the ADC’s internal reference and reference

buffer do not power down between conversions, elimi-

nating the need to wait for the reference to power up

before performing the next conversion. Shutdown mode

powers down the reference and reference buffer after

8 _______________________________________________________________________________________

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