Low-Power, 90Msps, Dual 6-Bit ADC
0.1µF
_IN+
VSOURCE
_IN-
0.1µF
20k
0.22µF
_OCC+
_OCC-
OFFSET
CORREC-
TION
INPUT
AMP
20k
MAX1003
2.35V INTERNAL REFERENCE
Figure 2. Single-Ended AC-Coupled Input
OFFSET CORRECTION DISABLED
_OCC+ _OCC-
OFFSET
CORREC-
TION
_IN+
VSOURCE
_IN-
20k
VREF
1.75V TO 2.75V
INPUT
AMP
20k
MAX1003
2.35V INTERNAL REFERENCE
0.1µF _IN+
VSOURCE
_IN-
0.1µF
20k
0.22µF
_OCC+
_OCC-
OFFSET
CORREC-
TION
INPUT
AMP
20k
MAX1003
2.35V INTERNAL REFERENCE
Figure 3. Differential AC-Coupled Input
OFFSET CORRECTION DISABLED
_OCC+ _OCC-
OFFSET
CORREC-
TION
_IN+
VSOURCE
_IN-
20k
DIFFERENTIAL SOURCE
WITH COMMON MODE
FROM 1.75V TO 2.75V.
INPUT
AMP
20k
MAX1003
2.35V INTERNAL REFERENCE
Figure 4. Single-Ended DC-Coupled Input
Figure 5. Differential DC-Coupled Input
For applications where a DC component of the input
signal is present, Figures 4 and 5 show single-ended
and differential DC-coupled input circuits. The ampli-
fiers’ input common-mode voltage range extends from
1.75V to 2.75V. To prevent attenuation of the input
signal’s DC component in this mode, disable the offset-
correction amplifier by grounding the _OCC+ and
_OCC- pins for the I and Q blocks (Figures 4 and 5).
ADCs
The I and Q ADC blocks receive the analog signals
from the respective I and Q input amplifiers. The ADCs
use flash conversion with 63 fully differential compara-
tors to digitize the analog input signal into a 6-bit output
in offset binary format.
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