5962-9054301MQA Просмотр технического описания (PDF) - Intersil

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5962-9054301MQA

CMOS High Performance Programmable DMA Controller

Intersil 

82C37A

received, addresses and control signals are generated by

the DMA controller to accomplish the DMA transfers. Data is

transferred directly from the I/O device to memory (or vice

versa) with IOR and MEMW (or MEMR and IOW) being

active. Note that data is not read into or driven out of the

DMA controller in I/O-to-memory or memory-to-I/O data

transfers.

82C84A

OR

82C85

CLK

HLDA

HLDA

HRQ

AX

ALE

AD0

M/IO

RD

WR

AD7

MN/MX

VCC

80C88

MEMR

MEMCS

DECODER

ADDRESS BUS

STB

OE

OE

82C82

VCC

47kΩ

DATA BUS

STB

82C82

ADDRESS BUS

MEMW

IOR

MEMCS

IOW MEMR

MEMW

MEMORY

DATA BUS

NOTE: The address lines need pull-up resistors.

FIGURE 6. APPLICATION FOR DMA SYSTEM

VCC

82C37A

CLK

EOP

CS

HLDA

ADSTB IOR

AEN

IOW

MEMR

MEMW

A0-7

HRQ

DB0-7 DREQ0

DACK

CS

DREQ

I/O

DEVICE

IOR

IOW

13

FN2967.2

March 20, 2006

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