Philips Semiconductors
Quadruple 2-input NOR gate
Product specification
HEF4001UB
gates
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
V
SYMBOL TYP. MAX.
Propagation delays
In → On
HIGH to LOW
LOW to HIGH
Output transition times
HIGH to LOW
LOW to HIGH
Input capacitance
5
65
130
10
tPHL
30
60
15
25
50
5
40
80
10
tPLH
20
40
15
15
30
5
75
150
10
tTHL
30
60
15
20
40
5
60
110
10
tTLH
30
60
15
20
40
CIN
−
10
TYPICAL EXTRAPOLATION
FORMULA
ns 30 ns + (0,70 ns/pF) CL
ns 17 ns + (0,27 ns/pF) CL
ns 15 ns + (0,20 ns/pF) CL
ns 13 ns + (0,55 ns/pF) CL
ns
9 ns + (0,23 ns/pF) CL
ns
7 ns + (0,16 ns/pF) CL
ns 15 ns + (1,20 ns/pF) CL
ns
6 ns + (0,48 ns/pF) CL
ns
4 ns + (0,32 ns/pF) CL
ns 10 ns + (1,00 ns/pF) CL
ns
9 ns + (0,42 ns/pF) CL
ns
6 ns + (0,28 ns/pF) CL
pF
VDD
V
TYPICAL FORMULA FOR P (µW)
Dynamic power
5
dissipation per
10
package (P)
15
500 fi + ∑ (foCL) × VDD2
5000 fi + ∑ (foCL) × VDD2
30 000 fi + ∑ (foCL) × VDD2
where
fi = input freq. (MHz)
fo = output freq. (MHz)
CL = load capacitance (pF)
∑(foCL) = sum of outputs
VDD = supply voltage (V)
January 1995
3