GS816236B-133I Просмотр технического описания (PDF) - Giga Semiconductor

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Компоненты Описание

производитель

GS816236B-133I

1M x 18, 512K x 36, 256K x 72 18Mb Sync Burst SRAMs

Giga Semiconductor 

GS816218(B/D)/GS816236(B/D)/GS816272(C)

JTAG Port Recommended Operating Conditions and DC Characteristics

Parameter

Symbol

Min.

Max.

Unit Notes

3.3 V Test Port Input High Voltage

VIHJ3

2.0

VDD3 +0.3

V

1

3.3 V Test Port Input Low Voltage

VILJ3

–0.3

0.8

V

1

2.5 V Test Port Input High Voltage

VIHJ2

0.6 * VDD2

VDD2 +0.3

V

1

2.5 V Test Port Input Low Voltage

VILJ2

–0.3

0.3 * VDD2

V

1

TMS, TCK and TDI Input Leakage Current

IINHJ

–300

1

uA

2

TMS, TCK and TDI Input Leakage Current

IINLJ

–1

100

uA

3

TDO Output Leakage Current

IOLJ

–1

1

uA

4

Test Port Output High Voltage

VOHJ

1.7

—

V 5, 6

Test Port Output Low Voltage

Test Port Output CMOS High

VOLJ

—

0.4

VOHJC VDDQ – 100 mV

—

V 5, 7

V 5, 8

Test Port Output CMOS Low

VOLJC

—

100 mV

V 5, 9

Notes:

1. Input Under/overshoot voltage must be –2 V > Vi < VDDn +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tTKC.

2. VILJ ≤ VIN ≤ VDDn

3. 0 V ≤ VIN ≤ VILJn

4. Output Disable, VOUT = 0 to VDDn

5. The TDO output driver is served by the VDDQ supply.

6. IOHJ = –4 mA

7. IOLJ = + 4 mA

8. IOHJC = –100 uA

9. IOHJC = +100 uA

JTAG Port AC Test Conditions

Parameter

Conditions

Input high level

VDD – 0.2 V

Input low level

0.2 V

Input slew rate

1 V/ns

Input reference level

VDDQ/2

Output reference level

VDDQ/2

Notes:

1. Include scope and jig capacitance.

2. Test conditions as shown unless otherwise noted.

JTAG Port AC Test Load

DQ

50Ω

30pF*

VDDQ/2

* Distributed Test Jig Capacitance

Rev: 2.17 11/2004

32/41

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

© 1999, GSI Technology

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