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October 1999
1.0 Features
• Dual phase-locked loop (PLL) device with three out-
put clock frequencies
• 3.3V supply voltage
• Small circuit board footprint (8-pin 0.150″ SOIC)
• Custom frequency selections available - contact your
local AMI Sales Representative for more information
Figure 1: Pin Configuration
CLKA 1
VSS 2
XIN 3
XOUT 4
8 SEL
7 VDD
6 CLKC
5 CLKB
8-pin (0.150″) SOIC
2.0 Description
The FS6285 is a monolithic CMOS clock generator IC
designed to minimize cost and component count in digital
video/audio systems.
Two high-resolution phase-locked loops generate two
output clocks (CLKA and CLKB) through an array of post-
dividers. All frequencies are ratiometrically derived from
the crystal oscillator frequency. The locking of all the out-
put frequencies together can eliminate unpredictable ar-
tifacts in video systems and reduce electromagnetic in-
terference (EMI) due to frequency harmonic stacking.
Table 1: Crystal / Output Frequencies
DEVICE fXIN (MHz) CLKA (MHz) CLKB (MHz) CLKC (MHz)
66.004(SEL=VSS)
FS6285-03
24.576
(fXIN* 188 / 70)
83.002(SEL=VDD)
(fXIN* 179 / 53)
NOTE: Contact AMI for custom PLL frequencies
14.3182
(fXIN* 67 / 115)
24.576
(fXIN)
Figure 2: Block Diagram
XIN
XOUT
CRYSTAL
OSC.
SEL
CLKA
PLL
DIVIDER
ARRAY
CLKB
PLL
CLKC
FS6285
10.1.99
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