11257-814 Просмотр технического описания (PDF) - AMI Semiconductor

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11257-814

Low-Skew Clock Fanout Buffer ICs

AMI Semiconductor 

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April 1999

8.0 Application Information

8.1 Reduction of EMI

The primary concern when designing the board layout for

this device is the reduction of electromagnetic interfer-

ence (EMI) generated by the 18 copies of the 100MHz

SDRAM clock. It is assumed the reader is familiar with

basic transmission line theory.

8.1.1 Layout Guidelines

To obtain the best performance, noise should be mini-

mized on the power and ground supplies to the IC. Ob-

serve good high-speed board design practices, such as:

 Use multi-layer circuit boards with dedicated low im-

pedance power and ground planes for the device

(denoted as CLK VDD and CLK GND in Figure 18).

The device power and ground planes should be

completely isolated from the motherboard power and

ground planes by a void in the power planes.

 Several low-pass filters using low impedance ferrite

EHDGV  DW 0+] DUH UHFRPPHQGHG WR GHFRu-

ple the device power and ground planes from the

motherboard power and ground planes (MB VDD and

MB GND). The beads should span the gap between

the power and ground planes. Seven beads for

power and seven beads for ground are suggested

(14 total) so that the clock rise times (1V/ns) can be

maintained.

 Place 1000pF bypass capacitors as close as possible

to the power pins of the IC. Use RF-quality low-

inductance multi-layer ceramic chip capacitors. Six

capacitors is optimal, one on each power/ground

grouping as shown in Figure 18.

 Load similar clock outputs equally, and keep output

loading as light as possible to help reduce clock skew

and power dissipation.

 Use equal-length clock traces that are as short as

possible. Rounded trace corners help reduce reflec-

tions and ringing in the clock signal.

 The clock traces must never cross the void area be-

tween power/ground planes. Each trace must have a

complete plane (either VDD or GND) under the com-

plete length of the trace.

Figure 18: Board Layout

VOID

1

2

RS

4

RS

5

1000pF

RS

8

RS

9

11

RS

13

RS

14

1000pF

RS

17

RS

18

1000pF

RS

21

CLK GND

MB GND

48

47

45

RS

44

RS

1000pF

41

RS

40

RS

38

36

RS

35

RS

1000pF

32

RS

31

RS

1000pF

28

RS

24

25

MB VDD

CLK VDD

Component

Layer

MB GND

MB VDD

CLK GND

CLK VDD

Signal Layer

MB GND

MB VDD

8.1.2 Output Driver Termination

A signal reflection will occur at any point on a PC-board

trace where impedance mismatches exist. Reflections

cause several undesirable effects in high-speed applica-

tions, such as an increase in clock jitter and a rise in

electromagnetic emissions from the board. Using a prop-

erly designed series termination on each high-speed line

can alleviate these problems by eliminating signal reflec-

tions.

Figure 19: Series Termination

DRIVER

zO

RS

LINE

zL

RECEIVE

4.5.99

,62

18

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