AD6657(Rev0) Просмотр технического описания (PDF) - Analog Devices

Номер в каталоге

Компоненты Описание

производитель

AD6657
(Rev.:Rev0)

Quad IF Receiver

Analog Devices 

AD6657

DIGITAL OUTPUTS

The AD6657 output drivers are configured to interface with

LVDS outputs using a DRVDD supply voltage of 1.8 V. The

output bits are DDR LVDS as shown in Figure 2. Applications

that require the ADC to drive large capacitive loads or large

fanouts may require external buffers or latches.

As described in Application Note AN-877, Interfacing to High

Speed ADCs via SPI, the data format can be selected for offset

binary or twos complement when using the SPI control.

TIMING

The AD6657 provides latched data with a pipeline delay of

nine clock cycles. Data outputs are available one propagation

delay (tPD) after the rising edge of the clock signal.

The length of the output data lines and the loads placed on

them should be minimized to reduce transients within the

AD6657. These transients can degrade converter dynamic

performance.

The lowest typical conversion rate of the AD6657 is 40 MSPS.

At clock rates below 40 MSPS, dynamic performance can degrade.

Data Clock Output (DCO)

The AD6657 provides a data clock output (DCO) signal intended

for capturing the data in an external register. The output data

for Channel A and Channel C is valid on the rising edge of

DCO; the output data for Channel B and Channel D is valid

on the falling edge of DCO. See Figure 2 for a graphical timing

description.

Table 11. Output Data Format

Input (V)

Condition (V)

VIN+ − VIN−

< −VREF − 0.5 LSB

VIN+ − VIN−

= −VREF

VIN+ − VIN−

=0

VIN+ − VIN−

= +VREF − 1.0 LSB

VIN+ − VIN−

> +VREF − 0.5 LSB

Offset Binary Output Mode

0000 0000 0000 0000

0000 0000 0000 0000

1000 0000 0000 0000

1111 1111 1111 1111

1111 1111 1111 1111

Twos Complement Mode

1000 0000 0000 0000

1000 0000 0000 0000

0000 0000 0000 0000

0111 1111 1111 1111

0111 1111 1111 1111

Rev. 0 | Page 21 of 32

Share Link: